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[src/trunk]: src/sys/arch/arm/sociox reorder functions for better relevance
details: https://anonhg.NetBSD.org/src/rev/52e10cd557a2
branches: trunk
changeset: 944743:52e10cd557a2
user: nisimura <nisimura%NetBSD.org@localhost>
date: Sat Oct 10 03:29:48 2020 +0000
description:
reorder functions for better relevance
diffstat:
sys/arch/arm/sociox/if_scx.c | 783 ++++++++++++++++++++++--------------------
1 files changed, 411 insertions(+), 372 deletions(-)
diffs (truncated from 1089 to 300 lines):
diff -r c5c012799cf4 -r 52e10cd557a2 sys/arch/arm/sociox/if_scx.c
--- a/sys/arch/arm/sociox/if_scx.c Sat Oct 10 03:05:04 2020 +0000
+++ b/sys/arch/arm/sociox/if_scx.c Sat Oct 10 03:29:48 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_scx.c,v 1.22 2020/03/28 13:15:24 nisimura Exp $ */
+/* $NetBSD: if_scx.c,v 1.23 2020/10/10 03:29:48 nisimura Exp $ */
/*-
* Copyright (c) 2020 The NetBSD Foundation, Inc.
@@ -29,35 +29,24 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#define NOT_MP_SAFE 0
/*
* Socionext SC2A11 SynQuacer NetSec GbE driver
*
- * (possibly incorrect notes to be removed eventually)
- * - 32 byte descriptor for 64 bit paddr design.
- * - multiple rings seems available. There are special descriptor fields
- * to designify ring number from which to arrive or to which go.
- * - memory mapped EEPROM to hold MAC address. The rest of the area is
- * occupied by a set of ucode for two DMA engines and one packet engine.
- * - The size of frame address filter is 16 plus 16.
- * - The first slot is my own station address. Always enabled to perform
- * to identify oneself.
- * - 1~15 are for supplimental MAC addresses. Independently enabled for
- * use. Good to catch multicast. Byte-wise selective match available.
- * Use the mask to catch { 0x01, 0x00, 0x00 } and/or { 0x33, 0x33 }.
- * - 16~32 might be exact match without byte-mask.
- * - The size of multicast hash filter store is 64 bit.
- * - Socionext/Linaro "NetSec" code contains some constants left unexplained.
- * Fortunately, Intel/Altera CycloneV PDFs describe every detail of
- * "such the instance of" DW EMAC IP and most of them are likely applicable
- * to SC2A11 GbE.
- * - not known "NetSec" instanciates DW timestamp or builds its own.
- * - DW EMAC implmentation (0x20) is known 0x10.36
+ * Multiple Tx and Rx queues exist inside and dedicated descriptor
+ * fields specifies which queue is to use. Three internal micro-processors
+ * to handle incoming frames, outgoing frames and packet data crypto
+ * processing. uP programs are stored in an external flash memory and
+ * have to be loaded by device driver.
+ * NetSec uses Synopsys DesignWare Core EMAC. DWC implmentation
+ * regiter (0x20) is known to have 0x10.36 and feature register (0x1058)
+ * to report XX.XX.
*/
+#define NOT_MP_SAFE 0
+
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.22 2020/03/28 13:15:24 nisimura Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.23 2020/10/10 03:29:48 nisimura Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -84,8 +73,47 @@
#include <dev/acpi/acpivar.h>
#include <dev/acpi/acpi_intr.h>
+/* Socionext SC2A11 descriptor format */
+struct tdes {
+ uint32_t t0, t1, t2, t3;
+};
+
+struct rdes {
+ uint32_t r0, r1, r2, r3;
+};
+
+#define T0_OWN (1U<<31) /* desc is ready to Tx */
+#define T0_EOD (1U<<30) /* end of descriptor array */
+#define T0_DRID (24) /* 29:24 D-RID */
+#define T0_PT (1U<<21) /* 23:21 PT */
+#define T0_TRID (16) /* 20:16 T-RID */
+#define T0_FS (1U<<9) /* first segment of frame */
+#define T0_LS (1U<<8) /* last segment of frame */
+#define T0_CSUM (1U<<7) /* enable check sum offload */
+#define T0_SGOL (1U<<6) /* enable TCP segment offload */
+#define T0_TRS (1U<<4) /* 5:4 TRS */
+#define T0_IOC (0) /* XXX TBD interrupt when completed */
+/* T1 segment address 63:32 */
+/* T2 segment address 31:0 */
+/* T3 31:16 TCP segment length, 15:0 segment length to transmit */
+
+#define R0_OWN (1U<<31) /* desc is empty */
+#define R0_EOD (1U<<30) /* end of descriptor array */
+#define R0_SRID (24) /* 29:24 S-RID */
+#define R0_FR (1U<<23) /* FR */
+#define R0_ER (1U<<21) /* Rx error indication */
+#define R0_ERR (3U<<16) /* 18:16 receive error code */
+#define R0_TDRID (14) /* 15:14 TD-RID */
+#define R0_FS (1U<<9) /* first segment of frame */
+#define R0_LS (1U<<8) /* last segment of frame */
+#define R0_CSUM (3U<<6) /* 7:6 checksum status */
+#define R0_CERR (2U<<6) /* 0 (undone), 1 (found ok), 2 (bad) */
+/* R1 frame address 63:32 */
+/* R2 frame address 31:0 */
+/* R3 31:16 received frame length, 15:0 buffer length to receive */
+
/*
- * SC2A11 register block 0x100-0x1204?
+ * SC2A11 NetSec registers. 0x100 - 1204
*/
#define SWRESET 0x104
#define COMINIT 0x120
@@ -98,7 +126,7 @@
#define xINTBEN 0x23c /* INT_B enable */
#define xINTB_SET 0x240 /* bit to set */
#define xINTB_CLR 0x244 /* bit to clr */
-/* 0x00c-048 */ /* pkt,tls,s0,s1 SR/IE/SET/CLR */
+/* 0x00c - 048 */ /* pkt,tls,s0,s1 SR/IE/SET/CLR */
#define TXISR 0x400
#define TXIEN 0x404
#define TXI_SET 0x428
@@ -123,7 +151,7 @@
#define PKTENG 0x0d0 /* packet engine ucode port */
#define CLKEN 0x100 /* clock distribution enable */
#define CLK_G (1U<<5)
-#define CLK_ALL 0x24
+#define CLK_ALL 0x13 /* 0x24 ??? */
#define MACADRH 0x10c /* ??? */
#define MACADRL 0x110 /* ??? */
#define MCVER 0x22c /* micro controller version */
@@ -140,6 +168,7 @@
/* 0xA00 */ /* enc RAW Rx SR/IE/SET/CLR */
/* 0xA40 */ /* dec RAW Rx SR/IE/SET/CLR */
+/* indirect GMAC registers. accessed thru MACCMD/MACDATA operation */
#define MACCMD 0x11c4 /* gmac operation */
#define CMD_IOWR (1U<<28) /* write op */
#define CMD_BUSY (1U<<31) /* busy bit */
@@ -150,7 +179,8 @@
#define DESC_SRST 0x1204 /* desc engine sw reset */
/*
- * GMAC register block. use mac_write()/mac_read() to handle
+ * GMAC registers. not memory mapped, but handled by indirect access.
+ * Mostly identical to Synopsys DesignWare Core Ethernet.
*/
#define GMACMCR 0x0000 /* MAC configuration */
#define MCR_IBN (1U<<30) /* ??? */
@@ -183,8 +213,6 @@
#define AFR_MHTE (1U<<2) /* use multicast hash table */
#define AFR_UHTE (1U<<1) /* use hash table for unicast */
#define AFR_PR (1U<<0) /* run promisc mode */
-#define GMACMHTH 0x0008 /* 64bit multicast hash table 63:32 */
-#define GMACMHTL 0x000c /* 64bit multicast hash table 31:0 */
#define GMACGAR 0x0010 /* MDIO operation */
#define GAR_PHY (11) /* mii phy 15:11 */
#define GAR_REG (6) /* mii reg 10:6 */
@@ -193,8 +221,7 @@
#define GAR_BUSY (1U) /* busy bit */
#define GMACGDR 0x0014 /* MDIO rd/wr data */
#define GMACFCR 0x0018 /* 802.3x flowcontrol */
- /* 31:16 pause timer value */
- /* 5:4 pause timer threthold */
+/* 31:16 pause timer value, 5:4 pause timer threthold */
#define FCR_RFE (1U<<2) /* accept PAUSE to throttle Tx */
#define FCR_TFE (1U<<1) /* generate PAUSE to moderate Rx lvl */
#define GMACVTAG 0x001c /* VLAN tag control */
@@ -209,42 +236,37 @@
#define ISR_RX (1U<<5) /* Rx completed */
#define ISR_ANY (1U<<4) /* any of above 5-7 report */
#define ISR_LC (1U<<0) /* link status change detected */
-#define GMACMAH0 0x0040 /* MAC address 0 47:32 */
-#define GMACMAL0 0x0044 /* MAC address 0 31:0 */
-#define GMACMAH(i) ((i)*8+0x40) /* supplimental MAC addr 1 - 15 */
-#define GMACMAL(i) ((i)*8+0x44) /* bit 31 to use, 30 SA,
- * 29:24 byte-wise don'care */
+#define GMACMAH0 0x0040 /* my own MAC address 47:32 */
+#define GMACMAL0 0x0044 /* my own MAC address 31:0 */
+#define GMACMAH(i) ((i)*8+0x40) /* supplimental MAC addr 1-15 */
+#define GMACMAL(i) ((i)*8+0x44) /* 31:0 MAC address low part */
+/* MAH bit-31: slot in use, 30: SA to match, 29:24 byte-wise don'care */
+#define GMACAMAH(i) ((i)*8+0x800) /* supplimental MAC addr 16-31 */
+#define GMACAMAL(i) ((i)*8+0x804) /* 31: MAC address low part */
+/* MAH bit-31: slot in use, no other bit is effective */
+#define GMACMHTH 0x0008 /* 64bit multicast hash table 63:32 */
+#define GMACMHTL 0x000c /* 64bit multicast hash table 31:0 */
+#define GMACMHT(i) ((i)*4+0x500) /* 256-bit alternative mcast hash 0-7 */
+#define GMACVHT 0x0588 /* 16-bit VLAN tag hash */
#define GMACMIISR 0x00d8 /* resolved xMII link status */
- /* 3 link up detected
- * 2:1 resovled speed
- * 0 2.5Mhz (10Mbps)
- * 1 25Mhz (100Mbps)
- * 2 125Mhz (1000Mbps)
- * 1 full duplex detected */
-#define GMACEVCTL 0x0100 /* event counter control */
-#define GMACEVCNT(i) ((i)*4+0x114) /* event counter 0x114~284 */
-
-#define GMACMHT(i) ((i)*4+0x500) /* 256bit multicast hash table 0 - 7 */
-#define GMACVHT 0x0588 /* VLAN tag hash */
+/* 3: link up detected, 2:1 resovled speed (0/1/2), 1: fdx detected */
-/* 0x0700-0734 ??? */
-#define GMACAMAH(i) ((i)*8+0x800) /* supplimental MAC addr 16-31 */
-#define GMACAMAL(i) ((i)*8+0x804) /* bit 31 to use */
+/* 0x0700 - 0734 ??? */
-#define GMACBMR 0x1000 /* DMA bus mode control
- * 24 4PBL 8???
- * 23 USP
- * 22:17 RPBL
- * 16 fixed burst, or undefined b.
- * 15:14 priority between Rx and Tx
- * 3 rxtx ratio 41
- * 2 rxtx ratio 31
- * 1 rxtx ratio 21
- * 0 rxtx ratio 11
- * 13:8 PBL possible DMA burst len
- * 7 alternative des8
- * 0 reset op. self clear
- */
+#define GMACBMR 0x1000 /* DMA bus mode control */
+/* 24 4PBL 8???
+ * 23 USP
+ * 22:17 RPBL
+ * 16 fixed burst, or undefined b.
+ * 15:14 priority between Rx and Tx
+ * 3 rxtx ratio 41
+ * 2 rxtx ratio 31
+ * 1 rxtx ratio 21
+ * 0 rxtx ratio 11
+ * 13:8 PBL packet burst len
+ * 7 alternative des8
+ * 0 reset op. (SC)
+ */
#define _BMR 0x00412080 /* XXX TBD */
#define _BMR0 0x00020181 /* XXX TBD */
#define BMR_RST (1) /* reset op. self clear when done */
@@ -252,8 +274,8 @@
#define GMACRPD 0x1008 /* write any to resume rdes */
#define GMACRDLA 0x100c /* rdes base address 32bit paddr */
#define GMACTDLA 0x1010 /* tdes base address 32bit paddr */
-#define _RDLA 0x18000 /* XXX TBD system SRAM with CC ? */
-#define _TDLA 0x1c000 /* XXX TBD system SRAM with CC ? */
+#define _RDLA 0x18000 /* XXX TBD system SRAM ? */
+#define _TDLA 0x1c000 /* XXX TBD system SRAM ? */
#define GMACDSR 0x1014 /* DMA status detail report; W1C */
#define GMACOMR 0x1018 /* DMA operation */
#define OMR_TSF (1U<<25) /* 1: Tx store&forword, 0: immed. */
@@ -267,55 +289,45 @@
#define GMACRWDT 0x1024 /* receive watchdog timer count */
#define GMACAXIB 0x1028 /* AXI bus mode control */
#define GMACAXIS 0x102c /* AXI status report */
-/* 0x1048-1054 */ /* descriptor and buffer cur. address */
+/* 0x1048 - 1054 */ /* descriptor and buffer cur. address */
#define HWFEA 0x1058 /* feature report */
-/* descriptor format definition */
-struct tdes {
- uint32_t t0, t1, t2, t3;
-};
-
-struct rdes {
- uint32_t r0, r1, r2, r3;
-};
+#define GMACEVCTL 0x0100 /* event counter control */
+#define GMACEVCNT(i) ((i)*4+0x114) /* event counter 0x114 - 0x284 */
-#define T0_OWN (1U<<31) /* desc is ready to Tx */
-#define T0_EOD (1U<<30) /* end of descriptor array */
-#define T0_DRID (24) /* 29:24 D-RID */
-#define T0_PT (1U<<21) /* 23:21 PT */
-#define T0_TRID (16) /* 20:16 T-RID */
-#define T0_FS (1U<<9) /* first segment of frame */
-#define T0_LS (1U<<8) /* last segment of frame */
-#define T0_CSUM (1U<<7) /* enable check sum offload */
-#define T0_SGOL (1U<<6) /* enable TCP segment offload */
-#define T0_TRS (1U<<4) /* 5:4 TRS */
-#define T0_IOC (0) /* XXX TBD interrupt when completed */
-/* T1 segment address 63:32 */
-/* T2 segment address 31:0 */
-/* T3 31:16 TCP segment length, 15:0 segment length to transmit */
-#define R0_OWN (1U<<31) /* desc is empty */
-#define R0_EOD (1U<<30) /* end of descriptor array */
-#define R0_SRID (24) /* 29:24 S-RID */
-#define R0_FR (1U<<23) /* FR */
-#define R0_ER (1U<<21) /* Rx error indication */
-#define R0_ERR (3U<<16) /* 18:16 receive error code */
-#define R0_TDRID (14) /* 15:14 TD-RID */
-#define R0_FS (1U<<9) /* first segment of frame */
-#define R0_LS (1U<<8) /* last segment of frame */
-#define R0_CSUM (3U<<6) /* 7:6 checksum status */
-#define R0_CERR (2U<<6) /* 0 (undone), 1 (found ok), 2 (bad) */
-/* R1 frame address 63:32 */
-/* R2 frame address 31:0 */
-/* R3 31:16 received frame length, 15:0 buffer length to receive */
+/* memory mapped CSR register */
+#define CSR_READ(sc,off) \
+ bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (off))
+#define CSR_WRITE(sc,off,val) \
+ bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (off), (val))
+
+/* flash memory access */
+#define EE_READ(sc,off) \
+ bus_space_read_4((sc)->sc_st, (sc)->sc_eesh, (off))
/*
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