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[src/trunk]: src/sys/arch Collapse all CPU_CORTEXA<n> options into CPU_CORTEX...
details: https://anonhg.NetBSD.org/src/rev/9fd6b91e3336
branches: trunk
changeset: 944469:9fd6b91e3336
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Tue Sep 29 19:58:49 2020 +0000
description:
Collapse all CPU_CORTEXA<n> options into CPU_CORTEX and do runtime
detection instead of ifdefs where required.
diffstat:
sys/arch/aarch64/conf/files.aarch64 | 5 +-
sys/arch/arm/arm32/arm32_tlb.c | 10 +--
sys/arch/arm/arm32/db_machdep.c | 27 ++-------
sys/arch/arm/conf/files.arm | 11 +---
sys/arch/arm/cortex/armperiph.c | 33 +-----------
sys/arch/arm/cortex/files.cortex | 6 +-
sys/arch/arm/imx/imx6_board.c | 6 +-
sys/arch/arm/include/cpuconf.h | 4 +-
sys/arch/arm/samsung/files.exynos | 6 +-
sys/arch/evbarm/beagle/beagle_machdep.c | 84 ++++++++++++++----------------
sys/arch/evbarm/conf/BCM5301X | 4 +-
sys/arch/evbarm/conf/BCM56340 | 4 +-
sys/arch/evbarm/conf/DUOVERO | 4 +-
sys/arch/evbarm/conf/GENERIC | 10 +--
sys/arch/evbarm/conf/GENERIC64 | 5 +-
sys/arch/evbarm/conf/KOBO | 4 +-
sys/arch/evbarm/conf/N900 | 4 +-
sys/arch/evbarm/conf/NETWALKER | 4 +-
sys/arch/evbarm/conf/OMAP5EVM | 4 +-
sys/arch/evbarm/conf/PANDABOARD | 4 +-
sys/arch/evbarm/conf/PARALLELLA | 3 +-
sys/arch/evbarm/conf/PEPPER | 4 +-
sys/arch/evbarm/conf/RPI2 | 4 +-
sys/arch/evbarm/conf/VTC100 | 4 +-
sys/arch/evbarm/conf/ZEDBOARD | 3 +-
sys/arch/evbarm/gumstix/gumstix_machdep.c | 58 +++++++++++---------
26 files changed, 123 insertions(+), 192 deletions(-)
diffs (truncated from 1007 to 300 lines):
diff -r f3bdc83780e7 -r 9fd6b91e3336 sys/arch/aarch64/conf/files.aarch64
--- a/sys/arch/aarch64/conf/files.aarch64 Tue Sep 29 19:41:48 2020 +0000
+++ b/sys/arch/aarch64/conf/files.aarch64 Tue Sep 29 19:58:49 2020 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.aarch64,v 1.27 2020/08/12 13:28:46 skrll Exp $
+# $NetBSD: files.aarch64,v 1.28 2020/09/29 19:58:49 jmcneill Exp $
defflag opt_cpuoptions.h AARCH64_ALIGNMENT_CHECK
defflag opt_cpuoptions.h AARCH64_EL0_STACK_ALIGNMENT_CHECK
@@ -8,9 +8,6 @@
defflag opt_cputypes.h CPU_ARMV8
defflag opt_cputypes.h CPU_CORTEX: CPU_ARMV8
-defflag opt_cputypes.h CPU_CORTEXA35: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA53: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA57: CPU_CORTEX
defflag opt_cputypes.h CPU_THUNDERX: CPU_ARMV8
# Interrupt implementation header definition
diff -r f3bdc83780e7 -r 9fd6b91e3336 sys/arch/arm/arm32/arm32_tlb.c
--- a/sys/arch/arm/arm32/arm32_tlb.c Tue Sep 29 19:41:48 2020 +0000
+++ b/sys/arch/arm/arm32/arm32_tlb.c Tue Sep 29 19:58:49 2020 +0000
@@ -31,7 +31,7 @@
#include "opt_multiprocessor.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.12 2018/08/15 06:00:02 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.13 2020/09/29 19:58:49 jmcneill Exp $");
#include <sys/param.h>
#include <sys/types.h>
@@ -143,7 +143,7 @@
return true;
}
-#if !defined(MULTIPROCESSOR) && defined(CPU_CORTEXA5)
+#if !defined(MULTIPROCESSOR)
static u_int
tlb_cortex_a5_record_asids(u_long *mapp, tlb_asid_t asid_max)
{
@@ -175,7 +175,7 @@
}
#endif
-#if !defined(MULTIPROCESSOR) && defined(CPU_CORTEXA7)
+#if !defined(MULTIPROCESSOR)
static u_int
tlb_cortex_a7_record_asids(u_long *mapp, tlb_asid_t asid_max)
{
@@ -212,14 +212,10 @@
tlb_record_asids(u_long *mapp, tlb_asid_t asid_max)
{
#ifndef MULTIPROCESSOR
-#ifdef CPU_CORTEXA5
if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid))
return tlb_cortex_a5_record_asids(mapp, asid_max);
-#endif
-#ifdef CPU_CORTEXA7
if (CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid))
return tlb_cortex_a7_record_asids(mapp, asid_max);
-#endif
#endif /* MULTIPROCESSOR */
#ifdef DIAGNOSTIC
mapp[0] = 0xfffffffe;
diff -r f3bdc83780e7 -r 9fd6b91e3336 sys/arch/arm/arm32/db_machdep.c
--- a/sys/arch/arm/arm32/db_machdep.c Tue Sep 29 19:41:48 2020 +0000
+++ b/sys/arch/arm/arm32/db_machdep.c Tue Sep 29 19:58:49 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.c,v 1.35 2020/08/14 16:18:36 skrll Exp $ */
+/* $NetBSD: db_machdep.c,v 1.36 2020/09/29 19:58:49 jmcneill Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe
@@ -34,7 +34,7 @@
#endif
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.35 2020/08/14 16:18:36 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.36 2020/09/29 19:58:49 jmcneill Exp $");
#include <sys/param.h>
@@ -135,11 +135,9 @@
{ DDB_ADD_CMD("reset", db_reset_cmd, 0,
"Reset the system",
NULL,NULL) },
-#if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7)
{ DDB_ADD_CMD("tlb", db_show_tlb_cmd, 0,
"Displays the TLB",
NULL,NULL) },
-#endif
#endif /* _KERNEL */
{ DDB_ADD_CMD(NULL, NULL, 0,NULL,NULL,NULL) }
@@ -220,7 +218,6 @@
cpu_reset_address();
}
-#if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7)
static void
tlb_print_common_header(const char *str)
{
@@ -257,7 +254,6 @@
u_int dti_index;
};
-#if defined(CPU_CORTEXA5)
static void
tlb_print_cortex_a5_header(void)
{
@@ -315,9 +311,7 @@
.dti_print_entry = tlb_print_cortex_a5_entry,
.dti_index = ARM_A5_TLBDATAOP_INDEX,
};
-#endif /* CPU_CORTEXA5 */
-#if defined(CPU_CORTEXA7)
static const char tlb_cortex_a7_esizes[8][8] = {
" 4KB(S)", " 4KB(L)", "64KB(S)", "64KB(L)",
" 1MB(S)", " 2MB(L)", "16MB(S)", " 1GB(L)",
@@ -394,29 +388,18 @@
.dti_print_entry = tlb_print_cortex_a7_entry,
.dti_index = ARM_A7_TLBDATAOP_INDEX,
};
-#endif /* CPU_CORTEXA7 */
static inline const struct db_tlbinfo *
tlb_lookup_tlbinfo(void)
{
-#if defined(CPU_CORTEXA5) && defined(CPU_CORTEXA7)
const bool cortex_a5_p = CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid);
const bool cortex_a7_p = CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid);
-#elif defined(CPU_CORTEXA5)
- const bool cortex_a5_p = true;
-#else
- const bool cortex_a7_p = true;
-#endif
-#ifdef CPU_CORTEXA5
if (cortex_a5_p) {
return &tlb_cortex_a5_info;
}
-#endif
-#ifdef CPU_CORTEXA7
if (cortex_a7_p) {
return &tlb_cortex_a7_info;
}
-#endif
return NULL;
}
@@ -425,6 +408,11 @@
{
const struct db_tlbinfo * const dti = tlb_lookup_tlbinfo();
+ if (dti == NULL) {
+ db_printf("not supported on this CPU\n");
+ return;
+ }
+
if (have_addr) {
const vaddr_t vpn = (vaddr_t)addr >> L2_S_SHIFT;
const u_int va_index = vpn & dti->dti_index;
@@ -468,7 +456,6 @@
}
db_printf("%zu TLB valid entries found\n", n);
}
-#endif /* CPU_CORTEXA5 || CPU_CORTEXA7 */
#if defined(MULTIPROCESSOR)
void
diff -r f3bdc83780e7 -r 9fd6b91e3336 sys/arch/arm/conf/files.arm
--- a/sys/arch/arm/conf/files.arm Tue Sep 29 19:41:48 2020 +0000
+++ b/sys/arch/arm/conf/files.arm Tue Sep 29 19:58:49 2020 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.arm,v 1.161 2020/08/02 06:58:16 maxv Exp $
+# $NetBSD: files.arm,v 1.162 2020/09/29 19:58:49 jmcneill Exp $
# temporary define to allow easy moving to ../arch/arm/arm32
defflag ARM32
@@ -40,15 +40,6 @@
defflag opt_cputypes.h CPU_ARM11MPCORE: CPU_ARM11
defflag opt_cputypes.h CPU_PJ4B: CPU_ARMV7
defflag opt_cputypes.h CPU_CORTEX: CPU_ARMV7
-defflag opt_cputypes.h CPU_CORTEXA5: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA7: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA8: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA9: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA15: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA17: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA35: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA53: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA57: CPU_CORTEX
defflag opt_cputypes.h FPU_VFP
defparam opt_cpuoptions.h XSCALE_CCLKCFG
diff -r f3bdc83780e7 -r 9fd6b91e3336 sys/arch/arm/cortex/armperiph.c
--- a/sys/arch/arm/cortex/armperiph.c Tue Sep 29 19:41:48 2020 +0000
+++ b/sys/arch/arm/cortex/armperiph.c Tue Sep 29 19:58:49 2020 +0000
@@ -32,7 +32,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.15 2018/09/25 20:55:34 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.16 2020/09/29 19:58:50 jmcneill Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -61,7 +61,6 @@
bus_size_t pi_off2;
};
-#ifdef CPU_CORTEXA5
static const struct armperiph_info a5_devices[] = {
{ "armscu", 0x0000, 0 },
{ "armgic", 0x1000, 0x0100 },
@@ -70,17 +69,13 @@
{ "arml2cc", 0, 0 }, /* external; needs "offset" property */
{ "", 0, 0 },
};
-#endif
-#ifdef CPU_CORTEXA7
static const struct armperiph_info a7_devices[] = {
{ "armgic", 0x1000, 0x2000 },
{ "armgtmr", 0, 0 },
{ "", 0, 0 },
};
-#endif
-#ifdef CPU_CORTEXA9
static const struct armperiph_info a9_devices[] = {
{ "armscu", 0x0000, 0 },
{ "arml2cc", 0x2000, 0 },
@@ -89,31 +84,24 @@
{ "a9wdt", 0x0600, 0 },
{ "", 0, 0 },
};
-#endif
-#ifdef CPU_CORTEXA15
static const struct armperiph_info a15_devices[] = {
{ "armgic", 0x1000, 0x2000 },
{ "armgtmr", 0, 0 },
{ "", 0, 0 },
};
-#endif
-#ifdef CPU_CORTEXA17
static const struct armperiph_info a17_devices[] = {
{ "armgic", 0x1000, 0x2000 },
{ "armgtmr", 0, 0 },
{ "", 0, 0 },
};
-#endif
-#ifdef CPU_CORTEXA57
static const struct armperiph_info a57_devices[] = {
{ "armgic", 0x1000, 0x2000 },
{ "armgtmr", 0, 0 },
{ "", 0, 0 },
};
-#endif
static const struct mpcore_config {
@@ -121,24 +109,12 @@
uint32_t cfg_cpuid;
uint32_t cfg_cbar_size;
} configs[] = {
-#ifdef CPU_CORTEXA5
{ a5_devices, 0x410fc050, 2*4096 },
-#endif
-#ifdef CPU_CORTEXA7
{ a7_devices, 0x410fc070, 8*4096 },
-#endif
-#ifdef CPU_CORTEXA9
{ a9_devices, 0x410fc090, 3*4096 },
-#endif
-#ifdef CPU_CORTEXA15
{ a15_devices, 0x410fc0f0, 8*4096 },
-#endif
-#ifdef CPU_CORTEXA17
{ a17_devices, 0x410fc0e0, 8*4096 },
-#endif
-#ifdef CPU_CORTEXA57
{ a57_devices, 0x410fd070, 8*4096 },
-#endif
};
static const struct mpcore_config *
@@ -230,15 +206,12 @@
.mpcaa_off1 = cfg->cfg_devices[i].pi_off1,
.mpcaa_off2 = cfg->cfg_devices[i].pi_off2,
};
-#if defined(CPU_CORTEXA9) || defined(CPU_CORTEXA5)
- if (strcmp(mpcaa.mpcaa_name, "arma9tmr") == 0)
+ if (strcmp(mpcaa.mpcaa_name, "arma9tmr") == 0) {
mpcaa.mpcaa_irq = IRQ_A9TMR_PPI_GTIMER;
-#endif
-#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA57)
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