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[src/trunk]: src/sys/dev/pci update register definitions from xsrc/external/m...



details:   https://anonhg.NetBSD.org/src/rev/55bb1ef6f95a
branches:  trunk
changeset: 944109:55bb1ef6f95a
user:      macallan <macallan%NetBSD.org@localhost>
date:      Fri Sep 18 20:43:37 2020 +0000

description:
update register definitions from xsrc/external/mit/xf86-video-ati/
merge in enough of the local changes to make radeonfb compile
tested on various macppc boxes

diffstat:

 sys/dev/pci/radeonfbreg.h |  3062 ++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 3008 insertions(+), 54 deletions(-)

diffs (truncated from 3550 to 300 lines):

diff -r 9bc0410bd179 -r 55bb1ef6f95a sys/dev/pci/radeonfbreg.h
--- a/sys/dev/pci/radeonfbreg.h Fri Sep 18 17:46:47 2020 +0000
+++ b/sys/dev/pci/radeonfbreg.h Fri Sep 18 20:43:37 2020 +0000
@@ -1,6 +1,4 @@
-/*     $NetBSD: radeonfbreg.h,v 1.7 2019/03/15 22:09:21 macallan Exp $ */
-
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.31 2003/11/10 18:41:23 tsi Exp $ */
+/*     $NetBSD: radeonfbreg.h,v 1.8 2020/09/18 20:43:37 macallan Exp $ */
 /*
  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
  *                VA Linux Systems Inc., Fremont, California.
@@ -30,14 +28,6 @@
  */
 
 /*
- * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and
- * does not endorse, this software.  ATI will not be responsible or liable
- * for any actual or alleged damage or loss caused by or in connection with
- * the use of or reliance on this software.
- */
-
-
-/*
  * Authors:
  *   Kevin E. Martin <martin%xfree86.org@localhost>
  *   Rickard E. Faith <faith%valinux.com@localhost>
@@ -68,6 +58,22 @@
 #define        RADEON_MAPREG_IO                0x14
 #define        RADEON_MAPREG_VRAM              0x10
 
+#define ATI_DATATYPE_VQ                                0
+#define ATI_DATATYPE_CI4                       1
+#define ATI_DATATYPE_CI8                       2
+#define ATI_DATATYPE_ARGB1555                  3
+#define ATI_DATATYPE_RGB565                    4
+#define ATI_DATATYPE_RGB888                    5
+#define ATI_DATATYPE_ARGB8888                  6
+#define ATI_DATATYPE_RGB332                    7
+#define ATI_DATATYPE_Y8                                8
+#define ATI_DATATYPE_RGB8                      9
+#define ATI_DATATYPE_CI16                      10
+#define ATI_DATATYPE_VYUY_422                  11
+#define ATI_DATATYPE_YVYU_422                  12
+#define ATI_DATATYPE_AYUV_444                  14
+#define ATI_DATATYPE_ARGB4444                  15
+
                                /* Registers for 2D/Video/Overlay */
 #define RADEON_ADAPTER_ID                   0x0f2c /* PCI */
 #define RADEON_AGP_BASE                     0x0170
@@ -86,6 +92,7 @@
 #       define RADEON_CAP_PTR_MASK          0xfc /* mask off reserved bits of CAP_PTR */
 #       define RADEON_CAP_ID_NULL           0x00 /* End of capability list */
 #       define RADEON_CAP_ID_AGP            0x02 /* AGP capability ID */
+#       define RADEON_CAP_ID_EXP            0x10 /* PCI Express */
 #define RADEON_AGP_COMMAND                  0x0f60 /* PCI */
 #define RADEON_AGP_COMMAND_PCI_CONFIG       0x0060 /* offset in PCI config*/
 #       define RADEON_AGP_ENABLE            (1<<8)
@@ -96,9 +103,15 @@
 #       define RADEON_AGP_4X_MODE           0x04
 #       define RADEON_AGP_FW_MODE           0x10
 #       define RADEON_AGP_MODE_MASK         0x17
+#       define RADEON_AGPv3_MODE            0x08
+#       define RADEON_AGPv3_4X_MODE         0x01
+#       define RADEON_AGPv3_8X_MODE         0x02
 #define RADEON_ATTRDR                       0x03c1 /* VGA */
 #define RADEON_ATTRDW                       0x03c0 /* VGA */
 #define RADEON_ATTRX                        0x03c0 /* VGA */
+#define RADEON_AUX_WINDOW_HORZ_CNTL         0x02d8
+#define RADEON_AUX_WINDOW_VERT_CNTL         0x02dc
+
 #define RADEON_AUX_SC_CNTL                  0x1660
 #       define RADEON_AUX1_SC_EN            (1 << 0)
 #       define RADEON_AUX1_SC_MODE_OR       (0 << 1)
@@ -126,13 +139,71 @@
 
 #define RADEON_BASE_CODE                    0x0f0b
 #define RADEON_BIOS_0_SCRATCH               0x0010
+#       define RADEON_FP_PANEL_SCALABLE     (1 << 16)
+#       define RADEON_FP_PANEL_SCALE_EN     (1 << 17)
+#       define RADEON_FP_CHIP_SCALE_EN      (1 << 18)
+#       define RADEON_DRIVER_BRIGHTNESS_EN  (1 << 26)
+#       define RADEON_DISPLAY_ROT_MASK      (3 << 28)
+#       define RADEON_DISPLAY_ROT_00        (0 << 28)
+#       define RADEON_DISPLAY_ROT_90        (1 << 28)
+#       define RADEON_DISPLAY_ROT_180       (2 << 28)
+#       define RADEON_DISPLAY_ROT_270       (3 << 28)
 #define RADEON_BIOS_1_SCRATCH               0x0014
 #define RADEON_BIOS_2_SCRATCH               0x0018
 #define RADEON_BIOS_3_SCRATCH               0x001c
 #define RADEON_BIOS_4_SCRATCH               0x0020
+#       define RADEON_CRT1_ATTACHED_MASK    (3 << 0)
+#       define RADEON_CRT1_ATTACHED_MONO    (1 << 0)
+#       define RADEON_CRT1_ATTACHED_COLOR   (2 << 0)
+#       define RADEON_LCD1_ATTACHED         (1 << 2)
+#       define RADEON_DFP1_ATTACHED         (1 << 3)
+#       define RADEON_TV1_ATTACHED_MASK     (3 << 4)
+#       define RADEON_TV1_ATTACHED_COMP     (1 << 4)
+#       define RADEON_TV1_ATTACHED_SVIDEO   (2 << 4)
+#       define RADEON_CRT2_ATTACHED_MASK    (3 << 8)
+#       define RADEON_CRT2_ATTACHED_MONO    (1 << 8)
+#       define RADEON_CRT2_ATTACHED_COLOR   (2 << 8)
+#       define RADEON_DFP2_ATTACHED         (1 << 11)
 #define RADEON_BIOS_5_SCRATCH               0x0024
+#       define RADEON_LCD1_ON               (1 << 0)
+#       define RADEON_CRT1_ON               (1 << 1)
+#       define RADEON_TV1_ON                (1 << 2)
+#       define RADEON_DFP1_ON               (1 << 3)
+#       define RADEON_CRT2_ON               (1 << 5)
+#       define RADEON_CV1_ON                (1 << 6)
+#       define RADEON_DFP2_ON               (1 << 7)
+#       define RADEON_LCD1_CRTC_MASK        (1 << 8)
+#       define RADEON_LCD1_CRTC_SHIFT       8
+#       define RADEON_CRT1_CRTC_MASK        (1 << 9)
+#       define RADEON_CRT1_CRTC_SHIFT       9
+#       define RADEON_TV1_CRTC_MASK         (1 << 10)
+#       define RADEON_TV1_CRTC_SHIFT        10
+#       define RADEON_DFP1_CRTC_MASK        (1 << 11)
+#       define RADEON_DFP1_CRTC_SHIFT       11
+#       define RADEON_CRT2_CRTC_MASK        (1 << 12)
+#       define RADEON_CRT2_CRTC_SHIFT       12
+#       define RADEON_CV1_CRTC_MASK         (1 << 13)
+#       define RADEON_CV1_CRTC_SHIFT        13
+#       define RADEON_DFP2_CRTC_MASK        (1 << 14)
+#       define RADEON_DFP2_CRTC_SHIFT       14
 #define RADEON_BIOS_6_SCRATCH               0x0028
+#       define RADEON_ACC_MODE_CHANGE       (1 << 2)
+#       define RADEON_EXT_DESKTOP_MODE      (1 << 3)
+#       define RADEON_LCD_DPMS_ON           (1 << 20)
+#       define RADEON_CRT_DPMS_ON           (1 << 21)
+#       define RADEON_TV_DPMS_ON            (1 << 22)
+#       define RADEON_DFP_DPMS_ON           (1 << 23)
+#       define RADEON_DPMS_MASK             (3 << 24)
+#       define RADEON_DPMS_ON               (0 << 24)
+#       define RADEON_DPMS_STANDBY          (1 << 24)
+#       define RADEON_DPMS_SUSPEND          (2 << 24)
+#       define RADEON_DPMS_OFF              (3 << 24)
+#       define RADEON_SCREEN_BLANKING       (1 << 26)
+#       define RADEON_DRIVER_CRITICAL       (1 << 27)
+#       define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)
 #define RADEON_BIOS_7_SCRATCH               0x002c
+#       define RADEON_SYS_HOTKEY            (1 << 10)
+#       define RADEON_DRV_LOADED            (1 << 12)
 #define RADEON_BIOS_ROM                     0x0f30 /* PCI */
 #define RADEON_BIST                         0x0f0f /* PCI */
 #define RADEON_BRUSH_DATA0                  0x1480
@@ -203,6 +274,7 @@
 #define RADEON_BRUSH_Y_X                    0x1474
 #define RADEON_BUS_CNTL                     0x0030
 #       define RADEON_BUS_MASTER_DIS         (1 << 6)
+#       define RADEON_BUS_BIOS_DIS_ROM       (1 << 12)
 #       define RADEON_BUS_RD_DISCARD_EN      (1 << 24)
 #       define RADEON_BUS_RD_ABORT_EN        (1 << 25)
 #       define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)
@@ -218,33 +290,77 @@
 #      define RADEON_BUS_MSTR_RD_MULT       (1 << 20)
 #      define RADEON_BUS_MSTR_RD_LINE       (1 << 21)
 #      define RADEON_BUS_RETRY_WS_SHIFT        16
-#       define RADEON_BUS_BIOS_DIS_ROM       (1 << 12)
 #define RADEON_BUS_CNTL1                    0x0034
 #       define RADEON_BUS_WAIT_ON_LOCK_EN    (1 << 4)
 
+#define RADEON_PCIE_INDEX                   0x0030
+#define RADEON_PCIE_DATA                    0x0034
+#define R600_PCIE_PORT_INDEX                0x0038
+#define R600_PCIE_PORT_DATA                 0x003c
+/* PCIE_LC_LINK_WIDTH_CNTL is PCIE on r1xx-r5xx, PCIE_PORT on r6xx-r7xx */
+#define RADEON_PCIE_LC_LINK_WIDTH_CNTL      0xa2 /* PCIE */
+#       define RADEON_PCIE_LC_LINK_WIDTH_SHIFT     0
+#       define RADEON_PCIE_LC_LINK_WIDTH_MASK      0x7
+#       define RADEON_PCIE_LC_LINK_WIDTH_X0        0
+#       define RADEON_PCIE_LC_LINK_WIDTH_X1        1
+#       define RADEON_PCIE_LC_LINK_WIDTH_X2        2
+#       define RADEON_PCIE_LC_LINK_WIDTH_X4        3
+#       define RADEON_PCIE_LC_LINK_WIDTH_X8        4
+#       define RADEON_PCIE_LC_LINK_WIDTH_X12       5
+#       define RADEON_PCIE_LC_LINK_WIDTH_X16       6
+#       define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT  4
+#       define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK   0x70
+#       define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE   (1 << 7)
+#       define RADEON_PCIE_LC_RECONFIG_NOW         (1 << 8)
+#       define RADEON_PCIE_LC_RECONFIG_LATER       (1 << 9)
+#       define RADEON_PCIE_LC_SHORT_RECONFIG_EN    (1 << 10)
+#       define R600_PCIE_LC_RENEGOTIATE_EN         (1 << 10)
+#       define R600_PCIE_LC_SHORT_RECONFIG_EN      (1 << 11)
+#define R600_TARGET_AND_CURRENT_PROFILE_INDEX      0x70c
+#define R700_TARGET_AND_CURRENT_PROFILE_INDEX      0x66c
+
 #define RADEON_CACHE_CNTL                   0x1724
 #define RADEON_CACHE_LINE                   0x0f0c /* PCI */
-#define RADEON_CAP0_TRIG_CNTL               0x0950 /* ? */
-#define RADEON_CAP1_TRIG_CNTL               0x09c0 /* ? */
 #define RADEON_CAPABILITIES_ID              0x0f50 /* PCI */
 #define RADEON_CAPABILITIES_PTR             0x0f34 /* PCI */
 #define RADEON_CLK_PIN_CNTL                 0x0001 /* PLL */
+#       define RADEON_DONT_USE_XTALIN       (1 << 4)
 #       define RADEON_SCLK_DYN_START_CNTL   (1 << 15)
 #define RADEON_CLOCK_CNTL_DATA              0x000c
 #define RADEON_CLOCK_CNTL_INDEX             0x0008
 #       define RADEON_PLL_WR_EN             (1 << 7)
 #       define RADEON_PLL_DIV_SEL           (3 << 8)
 #       define RADEON_PLL2_DIV_SEL_MASK     ~(3 << 8)
-#define RADEON_CLK_PWRMGT_CNTL              0x0014
+#define RADEON_M_SPLL_REF_FB_DIV            0x000a /* PLL */
+#       define RADEON_M_SPLL_REF_DIV_MASK   0xff
+#       define RADEON_M_SPLL_REF_DIV_SHIFT  0
+#       define RADEON_MPLL_FB_DIV_MASK      0xff
+#       define RADEON_MPLL_FB_DIV_SHIFT     8
+#       define RADEON_SPLL_FB_DIV_MASK      0xff
+#       define RADEON_SPLL_FB_DIV_SHIFT     16
+#define RADEON_SPLL_CNTL                    0x000c /* PLL */
+#       define RADEON_SPLL_SLEEP            (1 << 0)
+#       define RADEON_SPLL_RESET            (1 << 1)
+#       define RADEON_SPLL_PCP_MASK         0x7
+#       define RADEON_SPLL_PCP_SHIFT        8
+#       define RADEON_SPLL_PVG_MASK         0x7
+#       define RADEON_SPLL_PVG_SHIFT        11
+#       define RADEON_SPLL_PDC_MASK         0x3
+#       define RADEON_SPLL_PDC_SHIFT        14
+#define RADEON_CLK_PWRMGT_CNTL              0x0014 /* PLL */
 #       define RADEON_ENGIN_DYNCLK_MODE     (1 << 12)
 #       define RADEON_ACTIVE_HILO_LAT_MASK  (3 << 13)
 #       define RADEON_ACTIVE_HILO_LAT_SHIFT 13
 #       define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)
-#      define RADEON_MC_BUSY_MASK          (1 << 16)
-#      define RADEON_DLL_READY_MASK        (1 << 19)
+#       define RADEON_MC_BUSY               (1 << 16)
+#       define RADEON_DLL_READY             (1 << 19)
 #      define RADEON_CLK_PWRMGT_CNTL24     (1 << 24)
+#       define RADEON_CG_NO1_DEBUG_0        (1 << 24)
+#       define RADEON_CG_NO1_DEBUG_MASK     (0x1f << 24)
 #       define RADEON_DYN_STOP_MODE_MASK    (7 << 21)
-#define RADEON_PLL_PWRMGT_CNTL              0x0015
+#       define RADEON_TVPLL_PWRMGT_OFF      (1 << 30)
+#       define RADEON_TVCLK_TURNOFF         (1 << 31)
+#define RADEON_PLL_PWRMGT_CNTL              0x0015 /* PLL */
 #       define RADEON_TCL_BYPASS_DISABLE    (1 << 20)
 #define RADEON_CLR_CMP_CLR_3D               0x1a24
 #define RADEON_CLR_CMP_CLR_DST              0x15c8
@@ -268,7 +384,6 @@
 #       define RADEON_CFG_ATI_REV_A13       (2   << 16)
 #       define RADEON_CFG_ATI_REV_ID_MASK   (0xf << 16)
 #define RADEON_CONFIG_MEMSIZE               0x00f8
-#      define  RADEON_CONFIG_MEMSIZE_MASK  0x0fffffff
 #define RADEON_CONFIG_MEMSIZE_EMBEDDED      0x0114
 #define RADEON_CONFIG_REG_1_BASE            0x010c
 #define RADEON_CONFIG_REG_APER_SIZE         0x0110
@@ -325,9 +440,9 @@
 #      define RADEON_CRTC_PIX_WIDTH_8BPP   (2 <<  8)
 #      define RADEON_CRTC_PIX_WIDTH_32BPP  (6 <<  8)
 #      define RADEON_CRTC_PIX_WIDTH_MASK   (f <<  8)
+#       define RADEON_CRTC_ICON_EN          (1 << 15)
 #       define RADEON_CRTC_CUR_EN           (1 << 16)
-#       define RADEON_CRTC_CUR_MODE_MASK    (7 << 17)
-#       define RADEON_CRTC_ICON_EN          (1 << 20)
+#       define RADEON_CRTC_CUR_MODE_MASK    (7 << 20)
 #       define RADEON_CRTC_EXT_DISP_EN      (1 << 24)
 #       define RADEON_CRTC_EN               (1 << 25)
 #       define RADEON_CRTC_DISP_REQ_EN_B    (1 << 26)
@@ -338,6 +453,8 @@
 #       define RADEON_CRTC2_HSYNC_TRISTAT   (1 <<  5)
 #       define RADEON_CRTC2_VSYNC_TRISTAT   (1 <<  6)
 #       define RADEON_CRTC2_CRT2_ON         (1 <<  7)
+#       define RADEON_CRTC2_PIX_WIDTH_SHIFT 8
+#       define RADEON_CRTC2_PIX_WIDTH_MASK  (0xf << 8)
 #       define RADEON_CRTC2_ICON_EN         (1 << 15)
 #       define RADEON_CRTC2_CUR_EN          (1 << 16)
 #       define RADEON_CRTC2_CUR_MODE_MASK   (7 << 20)
@@ -348,9 +465,15 @@
 #       define RADEON_CRTC2_HSYNC_DIS       (1 << 28)
 #       define RADEON_CRTC2_VSYNC_DIS       (1 << 29)
 #define RADEON_CRTC_MORE_CNTL               0x27c
-#       define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)   
-#       define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)   
+#       define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2)
+#       define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3)
+#       define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
+#       define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
 #define RADEON_CRTC_GUI_TRIG_VLINE          0x0218
+#       define RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT  0
+#       define RADEON_CRTC_GUI_TRIG_VLINE_INV          (1 << 15)
+#       define RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT    16
+#       define RADEON_CRTC_GUI_TRIG_VLINE_STALL        (1 << 30)
 #define RADEON_CRTC_H_SYNC_STRT_WID         0x0204
 #       define RADEON_CRTC_H_SYNC_STRT_PIX        (0x07  <<  0)
 #       define RADEON_CRTC_H_SYNC_STRT_CHAR       (0x3ff <<  3)
@@ -375,13 +498,49 @@
 #       define RADEON_CRTC2_H_TOTAL_SHIFT   0
 #       define RADEON_CRTC2_H_DISP          (0x01ff << 16)
 #       define RADEON_CRTC2_H_DISP_SHIFT    16
+
+#define RADEON_CRTC_OFFSET_RIGHT           0x0220
 #define RADEON_CRTC_OFFSET                  0x0224
+#      define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)
+#      define RADEON_CRTC_OFFSET__OFFSET_LOCK     (1<<31)
+
 #define RADEON_CRTC2_OFFSET                 0x0324
+#      define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)
+#      define RADEON_CRTC2_OFFSET__OFFSET_LOCK     (1<<31)
 #define RADEON_CRTC_OFFSET_CNTL             0x0228
-#       define RADEON_CRTC_TILE_EN          (1 << 15)



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