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[src/trunk]: src/sys/arch/riscv Miscellaneous updates to reflect riscv-privil...



details:   https://anonhg.NetBSD.org/src/rev/a87f5d97e918
branches:  trunk
changeset: 945683:a87f5d97e918
user:      skrll <skrll%NetBSD.org@localhost>
date:      Wed Nov 04 06:56:56 2020 +0000

description:
Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@

diffstat:

 sys/arch/riscv/conf/GENERIC         |   6 +-
 sys/arch/riscv/conf/files.riscv     |   4 +-
 sys/arch/riscv/include/frame.h      |  10 ++--
 sys/arch/riscv/include/locore.h     |  16 +++---
 sys/arch/riscv/include/sysreg.h     |  85 ++++++++++++++++++++++++++++++------
 sys/arch/riscv/riscv/core_machdep.c |   4 +-
 sys/arch/riscv/riscv/db_machdep.c   |   4 +-
 sys/arch/riscv/riscv/genassym.cf    |  29 ++++++------
 sys/arch/riscv/riscv/locore.S       |  36 +++++----------
 sys/arch/riscv/riscv/trap.c         |  22 ++++----
 10 files changed, 129 insertions(+), 87 deletions(-)

diffs (truncated from 507 to 300 lines):

diff -r 9f910d033d14 -r a87f5d97e918 sys/arch/riscv/conf/GENERIC
--- a/sys/arch/riscv/conf/GENERIC       Wed Nov 04 06:24:44 2020 +0000
+++ b/sys/arch/riscv/conf/GENERIC       Wed Nov 04 06:56:56 2020 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.10 2019/06/01 12:42:27 maxv Exp $
+# $NetBSD: GENERIC,v 1.11 2020/11/04 06:56:56 skrll Exp $
 #
 # GENERIC machine description file
 #
@@ -22,12 +22,12 @@
 
 options        INCLUDE_CONFIG_FILE     # embed config file in kernel binary
 
-#ident                 "GENERIC-$Revision: 1.10 $"
+#ident                 "GENERIC-$Revision: 1.11 $"
 
 maxusers       64              # estimated number of users
 
 # Standard system options
-
+#options       FPE             # Floating-point extension support
 options        NTP             # NTP phase/frequency locked loop
 
 options        KTRACE          # system call tracing via ktrace(1)
diff -r 9f910d033d14 -r a87f5d97e918 sys/arch/riscv/conf/files.riscv
--- a/sys/arch/riscv/conf/files.riscv   Wed Nov 04 06:24:44 2020 +0000
+++ b/sys/arch/riscv/conf/files.riscv   Wed Nov 04 06:56:56 2020 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: files.riscv,v 1.6 2020/10/21 13:31:51 christos Exp $
+#      $NetBSD: files.riscv,v 1.7 2020/11/04 06:56:56 skrll Exp $
 #
 
 maxpartitions  16
@@ -14,7 +14,7 @@
 file   arch/riscv/riscv/db_disasm.c            ddb
 file   arch/riscv/riscv/db_trace.c             ddb
 file   arch/riscv/riscv/fixup.c
-file   arch/riscv/riscv/fpu.c
+file   arch/riscv/riscv/fpu.c                  fpe
 file   arch/riscv/riscv/ipifuncs.c             multiprocessor
 file   arch/riscv/riscv/stubs.c
 file   arch/riscv/riscv/syscall.c              # syscall handler
diff -r 9f910d033d14 -r a87f5d97e918 sys/arch/riscv/include/frame.h
--- a/sys/arch/riscv/include/frame.h    Wed Nov 04 06:24:44 2020 +0000
+++ b/sys/arch/riscv/include/frame.h    Wed Nov 04 06:56:56 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: frame.h,v 1.2 2020/03/14 16:12:16 skrll Exp $ */
+/* $NetBSD: frame.h,v 1.3 2020/11/04 06:56:56 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -36,10 +36,10 @@
 
 struct trapframe {
        struct reg tf_regs __aligned(8);
-       register_t tf_badvaddr;
-       register_t tf_pc;
-       uint32_t tf_cause;              // 32-bit register
-       uint32_t tf_sr;                 // 32-bit register
+       register_t tf_stval;            // supervisor trap value
+       register_t tf_sepc;             // supervisor exception program counter
+       register_t tf_scause;           // supervisor cause register
+       register_t tf_sr;               // supervisor status register
 #define tf_reg         tf_regs.r_reg
 #define tf_a0          tf_reg[_X_A0]
 #define tf_t0          tf_reg[_X_T0]
diff -r 9f910d033d14 -r a87f5d97e918 sys/arch/riscv/include/locore.h
--- a/sys/arch/riscv/include/locore.h   Wed Nov 04 06:24:44 2020 +0000
+++ b/sys/arch/riscv/include/locore.h   Wed Nov 04 06:56:56 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.5 2020/03/14 16:12:16 skrll Exp $ */
+/* $NetBSD: locore.h,v 1.6 2020/11/04 06:56:56 skrll Exp $ */
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -39,9 +39,9 @@
 
 struct trapframe {
        struct reg tf_regs;
-       register_t tf_badaddr;
-       uint32_t tf_cause;              // 32-bit register
-       uint32_t tf_sr;                 // 32-bit register
+       register_t tf_tval;
+       register_t tf_cause;
+       register_t tf_sr;
 #define tf_reg         tf_regs.r_reg
 #define tf_pc          tf_regs.r_pc
 #define tf_ra          tf_reg[_X_RA]
@@ -80,9 +80,9 @@
 // For COMPAT_NETBSD32 coredumps
 struct trapframe32 {
        struct reg32 tf_regs;
-       register32_t tf_badaddr;
-       uint32_t tf_cause;              // 32-bit register
-       uint32_t tf_sr;                 // 32-bit register
+       register32_t tf_tval;
+       register32_t tf_cause;
+       register32_t tf_sr;
 };
 
 #define FB_A0  0
@@ -105,7 +105,7 @@
 
 struct faultbuf {
        register_t fb_reg[FB_MAX];
-       uint32_t fb_sr;
+       register_t fb_sr;
 };
 
 CTASSERT(sizeof(label_t) == sizeof(struct faultbuf));
diff -r 9f910d033d14 -r a87f5d97e918 sys/arch/riscv/include/sysreg.h
--- a/sys/arch/riscv/include/sysreg.h   Wed Nov 04 06:24:44 2020 +0000
+++ b/sys/arch/riscv/include/sysreg.h   Wed Nov 04 06:56:56 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.8 2020/11/02 08:37:59 skrll Exp $ */
+/* $NetBSD: sysreg.h,v 1.9 2020/11/04 06:56:56 skrll Exp $ */
 
 /*
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -43,6 +43,7 @@
 #define FCSR_FRM_RDN   0b010   // Round DowN (-infinity)
 #define FCSR_FRM_RUP   0b011   // Round UP (+infinity)
 #define FCSR_FRM_RMM   0b100   // Round to nearest, ties to Max Magnitude
+#define FCSR_FRM_DYN   0b111   // Dynamic rounding
 #define FCSR_FFLAGS    __BITS(4,0)     // Sticky bits
 #define FCSR_NV                __BIT(4)        // iNValid operation
 #define FCSR_DZ                __BIT(3)        // Divide by Zero
@@ -101,25 +102,77 @@
        return __SHIFTOUT(__old, FCSR_FRM);
 }
 
-// Status Register
-#define SR_IP          __BITS(31,24)   // Pending interrupts
-#define SR_IM          __BITS(23,16)   // Interrupt Mask
-#define SR_VM          __BIT(7)        // MMU On
-#define SR_S64         __BIT(6)        // RV64 supervisor mode
-#define SR_U64         __BIT(5)        // RV64 user mode
-#define SR_EF          __BIT(4)        // Enable Floating Point
-#define SR_PEI         __BIT(3)        // Previous EI setting
-#define SR_EI          __BIT(2)        // Enable interrupts
-#define SR_PS          __BIT(1)        // Previous (S) supervisor setting
-#define SR_S           __BIT(0)        // Supervisor
+/* Supervisor Status Register */
+#ifdef _LP64
+#define SR_WPRI                __BITS(62, 34) | __BITS(31,20) | __BIT(17) | \
+                           __BITS(12,9) | __BITS(7,6) | __BITS(3,2)
+#define SR_SD          __BIT(63)
+                       /* Bits 62-34 are WPRI */
+#define SR_UXL         __BITS(33,32)
+#define  SR_UXL_32     1
+#define  SR_UXL_64     2
+#define  SR_UXL_128    3
+                       /* Bits 31-20 are WPRI*/
+#else
+#define SR_WPRI                __BITS(30,20) | __BIT(17) | __BITS(12,9) | \
+                           __BITS(7,6) | __BITS(3,2)
+#define SR_SD          __BIT(31)
+                       /* Bits 30-20 are WPRI*/
+#endif /* _LP64 */
+
+/* Both RV32 and RV64 have the bottom 20 bits shared */
+#define SR_MXR         __BIT(19)
+#define SR_SUM         __BIT(18)
+                       /* Bit 17 is WPRI */
+#define SR_XS          __BITS(16,15)
+#define SR_FS          __BITS(14,13)
+#define  SR_FS_OFF     0
+#define  SR_FS_INITIAL 1
+#define  SR_FS_CLEAN   2
+#define  SR_FS_DIRTY   3
+
+                       /* Bits 12-9 are WPRI */
+#define SR_SPP         __BIT(8)
+                       /* Bits 7-6 are WPRI */
+#define SR_SPIE                __BIT(5)
+#define SR_UPIE                __BIT(4)
+                       /* Bits 3-2 are WPRI */
+#define SR_SIE         __BIT(1)
+#define SR_UIE         __BIT(0)
+
+/* Supervisor interrupt registers */
+/* ... interupt pending register (sip) */
+                       /* Bit (XLEN-1)-10 is WIRI */
+#define SIP_SEIP       __BIT(9)
+#define SIP_UEIP       __BIT(8)
+                       /* Bit 7-6 is WIRI */
+#define SIP_STIP       __BIT(5)
+#define SIP_UTIP       __BIT(4)
+                       /* Bit 3-2 is WIRI */
+#define SIP_SSIP       __BIT(1)
+#define SIP_USIP       __BIT(0)
+
+/* ... interupt-enable register (sie) */
+                       /* Bit (XLEN-1) - 10 is WIRI */
+#define SIE_SEIE       __BIT(9)
+#define SIE_UEIE       __BIT(8)
+                       /* Bit 7-6 is WIRI */
+#define SIE_STIE       __BIT(5)
+#define SIE_UTIE       __BIT(4)
+                       /* Bit 3-2 is WIRI */
+#define SIE_SSIE       __BIT(1)
+#define SIE_USIE       __BIT(0)
+
+/* Mask for all interrupts */
+#define SIE_IM         (SIE_SEI|SIE_UEIE|SIE_STIE|SIE_UTIE|SIE_SSIE|SIE_USIE)
 
 #ifdef _LP64
-#define        SR_USER         (SR_EI|SR_U64|SR_S64|SR_VM|SR_IM)
+#define        SR_USER         (SR_UIE | SR_U64 | SR_S64 | SR_IM)
 #define        SR_USER32       (SR_USER & ~SR_U64)
-#define        SR_KERNEL       (SR_S|SR_EI|SR_U64|SR_S64|SR_VM)
+#define        SR_KERNEL       (SR_S | SR_UIE | SR_U64 | SR_S64)
 #else
-#define        SR_USER         (SR_EI|SR_VM|SR_IM)
-#define        SR_KERNEL       (SR_S|SR_EI|SR_VM)
+#define        SR_USER         (SR_UIE||SR_IM)
+#define        SR_KERNEL       (SR_S|SR_UIE)
 #endif
 
 static inline uint32_t
diff -r 9f910d033d14 -r a87f5d97e918 sys/arch/riscv/riscv/core_machdep.c
--- a/sys/arch/riscv/riscv/core_machdep.c       Wed Nov 04 06:24:44 2020 +0000
+++ b/sys/arch/riscv/riscv/core_machdep.c       Wed Nov 04 06:56:56 2020 +0000
@@ -30,7 +30,7 @@
 #include <sys/cdefs.h>
 
 #ifndef CORENAME
-__RCSID("$NetBSD: core_machdep.c,v 1.3 2019/11/20 19:37:52 pgoyette Exp $");
+__RCSID("$NetBSD: core_machdep.c,v 1.4 2020/11/04 06:56:56 skrll Exp $");
 #endif
 
 #include <sys/param.h>
@@ -81,7 +81,7 @@
                cpustate.tf.tf_reg[i] = tf->tf_reg[i];
        }
        cpustate.tf.tf_pc = tf->tf_pc;
-       cpustate.tf.tf_badaddr = tf->tf_badaddr;
+       cpustate.tf.tf_tval = tf->tf_tval;
        cpustate.tf.tf_cause = tf->tf_cause;
        cpustate.tf.tf_sr = tf->tf_sr;
        if (fpu_valid_p(l)) {
diff -r 9f910d033d14 -r a87f5d97e918 sys/arch/riscv/riscv/db_machdep.c
--- a/sys/arch/riscv/riscv/db_machdep.c Wed Nov 04 06:24:44 2020 +0000
+++ b/sys/arch/riscv/riscv/db_machdep.c Wed Nov 04 06:56:56 2020 +0000
@@ -29,7 +29,7 @@
 
 #include <sys/cdefs.h>
 
-__RCSID("$NetBSD: db_machdep.c,v 1.4 2020/03/14 16:12:16 skrll Exp $");
+__RCSID("$NetBSD: db_machdep.c,v 1.5 2020/11/04 06:56:56 skrll Exp $");
 
 #include <sys/param.h>
 
@@ -80,7 +80,7 @@
        { "pc", (void *)offsetof(struct trapframe, tf_pc), db_rw_ddbreg, NULL },
        { "status", (void *)offsetof(struct trapframe, tf_sr), db_rw_ddbreg, "i" },
        { "cause", (void *)offsetof(struct trapframe, tf_cause), db_rw_ddbreg, "i" },
-       { "badaddr", (void *)offsetof(struct trapframe, tf_badaddr), db_rw_ddbreg, NULL },
+       { "tval", (void *)offsetof(struct trapframe, tf_tval), db_rw_ddbreg, NULL },
 };
 const struct db_variable * const db_eregs = db_regs + __arraycount(db_regs);
 
diff -r 9f910d033d14 -r a87f5d97e918 sys/arch/riscv/riscv/genassym.cf
--- a/sys/arch/riscv/riscv/genassym.cf  Wed Nov 04 06:24:44 2020 +0000
+++ b/sys/arch/riscv/riscv/genassym.cf  Wed Nov 04 06:56:56 2020 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: genassym.cf,v 1.7 2020/01/08 17:38:42 ad Exp $
+#      $NetBSD: genassym.cf,v 1.8 2020/11/04 06:56:56 skrll Exp $
 #-
 # Copyright (c) 2014 The NetBSD Foundation, Inc.
 # All rights reserved.
@@ -47,17 +47,18 @@
 include <riscv/locore.h>
 include <riscv/sysreg.h>
 
-define SR_IM           SR_IM
-define SR_IM_LSHIFT    __SIZEOF_LONG__ * 8 - (ilog2(SR_IM) + 1)
-define SR_IM_RSHIFT    ilog2(__LOWEST_SET_BIT(SR_IM))
-define SR_VM           SR_VM
-define SR_U64          SR_U64
-define SR_S64          SR_S64
-define SR_EF           SR_EF
-define SR_PEI          SR_PEI
-define SR_EI           SR_EI
-define SR_PS           SR_PS
-define SR_S            SR_S
+#define        SR_IM           SR_IM
+#define        SR_IM_LSHIFT    __SIZEOF_LONG__ * 8 - (ilog2(SR_IM) + 1)
+#define        SR_IM_RSHIFT    ilog2(__LOWEST_SET_BIT(SR_IM))
+#define        SR_VM           SR_VM
+#define        SR_U64          SR_U64
+#define        SR_S64          SR_S64
+#define        SR_EF           SR_EF
+#define        SR_PEI          SR_PEI
+#define        SR_EI           SR_EI
+#define        SR_PS           SR_PS
+#define        SR_S            SR_S
+define SR_SIE          SR_SIE
 
 define CAUSE_SYSCALL   CAUSE_SYSCALL



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