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[src/trunk]: src/sys/dev/ic improve register descriptions



details:   https://anonhg.NetBSD.org/src/rev/4e0ffa3f2c73
branches:  trunk
changeset: 940249:4e0ffa3f2c73
user:      nisimura <nisimura%NetBSD.org@localhost>
date:      Thu Oct 08 11:29:04 2020 +0000

description:
improve register descriptions

diffstat:

 sys/dev/ic/dm9000reg.h |  174 +++++++++++++++++++++++++++---------------------
 1 files changed, 98 insertions(+), 76 deletions(-)

diffs (231 lines):

diff -r 4d847a0809f0 -r 4e0ffa3f2c73 sys/dev/ic/dm9000reg.h
--- a/sys/dev/ic/dm9000reg.h    Thu Oct 08 09:16:13 2020 +0000
+++ b/sys/dev/ic/dm9000reg.h    Thu Oct 08 11:29:04 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: dm9000reg.h,v 1.4 2020/03/31 02:32:25 nisimura Exp $   */
+/*     $NetBSD: dm9000reg.h,v 1.5 2020/10/08 11:29:04 nisimura Exp $   */
 
 /*
  * Copyright (c) 2009 Paul Fleischer
@@ -47,77 +47,92 @@
 
 #define DM9000_IOSIZE 4
 
-#define DM9000_NCR             0x00
+#define DM9000_NCR             0x00    /* "network" control */
 #define  DM9000_NCR_RST                (1<<0)  /* reset chip, self clear */
-#define  DM9000_NCR_LBK_MASK   (0x06)
+#define  DM9000_NCR_LBK_MASK   (0x06)  /* loopback test selection */
 #define  DM9000_NCR_LBK_SHIFT  (1)
-#define  DM9000_NCR_LBK_MAC_INTERNAL (1<<DM9000_NCR_LBK_SHIFT)
-#define  DM9000_NCR_LBK_NORMAL (0<<DM9000_NCR_LBK_SHIFT)
-#define  DM9000_NCR_LBK_INT_PHY (2<<DM9000_NCR_LBK_SHIFT)
-#define  DM9000_NCR_FDX                (1<<3)  /* activate PAUSE flow control */
-#define  DM9000_NCR_FCOL       (1<<4)
-#define  DM9000_NCR_WAKEEN     (1<<6)
-#define  DM9000_NCR_EXY_PHY    (1<<7)
-#define DM9000_NSR             0x01
+#define  DM9000_NCR_LBK_NORMAL (0<<1)  /* normal operation */
+#define  DM9000_NCR_LBK_MAC_INTERNAL (1<<1) /* MAC loopback */
+#define  DM9000_NCR_LBK_INT_PHY (2<<1) /* PHY loopback */
+#define  DM9000_NCR_FDX                (1<<3)  /* use full-duplex, RO when int PHY */
+#define  DM9000_NCR_FCOL       (1<<4)  /* force coll. mode. test only */
+#define  DM9000_NCR_WAKEEN     (1<<6)  /* wakeup event enable */
+#define  DM9000_NCR_EXY_PHY    (1<<7)  /* select ext. PHY, immune SW reset */
+#define DM9000_NSR             0x01    /* "network" status */
 #define  DM9000_NSR_RXOV       (1<<1)  /* receive overflow deteced */
-#define  DM9000_NSR_TX1END     (1<<2)  /* transmit 1 completed */
-#define  DM9000_NSR_TX2END     (1<<3)  /* transmit 2 completed */
-#define  DM9000_NSR_WAKEST     (1<<5)
-#define  DM9000_NSR_LINKST     (1<<6)  /* link up detected */
+#define  DM9000_NSR_TX1END     (1<<2)  /* transmit 1 completed, W1C */
+#define  DM9000_NSR_TX2END     (1<<3)  /* transmit 2 completed, W1C */
+#define  DM9000_NSR_WAKEST     (1<<5)  /* wakeup event, W1C */
+#define  DM9000_NSR_LINKST     (1<<6)  /* link is up */
 #define  DM9000_NSR_SPEED      (1<<7)  /* 1: 100Mbps, 0: 10Mbps */
-#define DM9000_TCR             0x02
+#define DM9000_TCR             0x02    /* Tx control */
 #define  DM9000_TCR_TXREQ      (1<<0)  /* request to start Tx, self clear */
-#define  DM9000_TCR_CRC_DIS1   (1<<1)
-#define  DM9000_TCR_PAD_DIS1   (1<<2)
-#define  DM9000_TCR_CRC_DIS2   (1<<3)
-#define  DM9000_TCR_PAD_DIS2   (1<<4)
-#define  DM9000_TCR_EXCECM     (1<<5)
-#define  DM9000_TCR_TJDIS      (1<<6)
+#define  DM9000_TCR_CRC_DIS1   (1<<1)  /* disable PAD op on Tx1 */
+#define  DM9000_TCR_PAD_DIS1   (1<<2)  /* disbale CRC append on Tx1 */
+#define  DM9000_TCR_CRC_DIS2   (1<<3)  /* disable PAD op on Tx2 */
+#define  DM9000_TCR_PAD_DIS2   (1<<4)  /* disbale CRC append on Tx2 */
+#define  DM9000_TCR_EXCECM     (1<<5)  /* allow infinate colli. retries */
+#define  DM9000_TCR_TJDIS      (1<<6)  /* disable xmit jabber, otherwise on */
 #define DM9000_TSR1            0x03    /* transmit completion status 1 */
 #define DM9000_TSR2            0x04    /* transmit completion status 2 */
-#define DM9000_RCR             0x05
+#define  DM9000_TSR_EC         (1<<2)  /* aborted after 16 collision */
+#define  DM9000_TSR_COL                (1<<3)  /* collision detected while xmit */
+#define  DM9000_TSR_LCOL       (1<<4)  /* out of window "late" collision */
+#define  DM9000_TSR_NC         (1<<5)  /* no carrier signal found */
+#define  DM9000_TSR_CLOSS      (1<<6)  /* loss of carrier */
+#define  DM9000_TSR_TJTO       (1<<7)  /* Tx jabber time out */
+#define DM9000_RCR             0x05    /* Rx control */
 #define  DM9000_RCR_RXEN       (1<<0)  /* activate Rx */
 #define  DM9000_RCR_PRMSC      (1<<1)  /* enable promisc mode */
-#define  DM9000_RCR_RUNT       (1<<2)  /* allow to receive runt frame */
+#define  DM9000_RCR_RUNT       (1<<2)  /* accept damaged runt frame */
 #define  DM9000_RCR_ALL                (1<<3)  /* accept all multicast */
 #define  DM9000_RCR_DIS_CRC    (1<<4)  /* drop bad CRC frame */
-#define  DM9000_RCR_DIS_LONG   (1<<5)  /* drop too long frame (>1522) */
-#define  DM9000_RCR_WTDIS      (1<<6)  /* disable Rx watchdog timer */
-#define DM9000_RSR             0x06
+#define  DM9000_RCR_DIS_LONG   (1<<5)  /* drop too long frame >1522 */
+#define  DM9000_RCR_WTDIS      (1<<6)  /* disable >2048 Rx detect timer */
+#define DM9000_RSR             0x06    /* Rx status */
 #define  DM9000_RSR_FOE                (1<<0)  /* Rx FIFO overflow detected */
-#define  DM9000_RSR_CE         (1<<1)
-#define  DM9000_RSR_AE         (1<<2)
-#define  DM9000_RSR_PLE                (1<<3)
-#define  DM9000_RSR_RWTO       (1<<4)
-#define  DM9000_RSR_LCS                (1<<5)
+#define  DM9000_RSR_CE         (1<<1)  /* CRC error found */
+#define  DM9000_RSR_AE         (1<<2)  /* tail not ended in byte boundary */
+#define  DM9000_RSR_PLE                (1<<3)  /* physical layer error */
+#define  DM9000_RSR_RWTO       (1<<4)  /* >2048 condition detected */
+#define  DM9000_RSR_LCS                (1<<5)  /* late colli. detected */
 #define  DM9000_RSR_MF         (1<<6)  /* mcast/bcast frame received */
-#define  DM9000_RSR_RF         (1<<7)  /* runt frame received (<64 bytes) */
-#define DM9000_ROCR            0x07
-#define DM9000_BPTR            0x08
-#define DM9000_FCTR            0x09
-#define DM9000_FCR             0x0A
+#define  DM9000_RSR_RF         (1<<7)  /* damaged runt frame received <64 */
+#define DM9000_ROCR            0x07    /* receive overflow counter */
+/* 7: OVF detected, 6:0 statistic couner */
+#define DM9000_BPTR            0x08    /* back pressure threshold */
+/* 7:4 back pressure high watermark (3 def), 3:0 jam pattern time (7 def) */
+#define DM9000_FCTR            0x09    /* flow control threshold */
+/* 7:4 Rx FIFO high w.m. (3 def), low w.m. (8 def) */
+#define DM9000_FCR             0x0A    /* Rx flow control */
 #define  DM9000_FCR_FLCE       (1<<0)  /* flow control enable */
 #define  DM9000_FCR_RXPCS      (1<<1)  /* Rx PAUSE current status */
-#define  DM9000_FCR_RXPS       (1<<2)  /* Rx PAUSE status, read to clear */
-#define  DM9000_FCR_BKPM       (1<<3)
-#define  DM9000_FCR_BKPA       (1<<4)
-#define  DM9000_FCR_TXPEN      (1<<5)  /* force PAUSE/unPAUSE */
-#define  DM9000_FCR_TXPF       (1<<6)  /* Tx PAUSE packet (when full */
+#define  DM9000_FCR_RXPS       (1<<2)  /* Rx PAUSE status, latched R2C */
+#define  DM9000_FCR_BKPM       (1<<3)  /* HDX back pressure for my frames */
+#define  DM9000_FCR_BKPA       (1<<4)  /* HDX back pressure for any frames */
+#define  DM9000_FCR_TXPEN      (1<<5)  /* activate auto PAUSE operation */
+#define  DM9000_FCR_TXPF       (1<<6)  /* Tx PAUSE packet (when full) */
 #define  DM9000_FCR_TXP0       (1<<7)  /* Tx PAUSE packet (when empty) */
-#define DM9000_EPCR            0x0B
+#define DM9000_EPCR            0x0B    /* EEPROM / PHY control */
 #define  DM9000_EPCR_ERRE      (1<<0)  /* operation in progress, busy bit */
-#define  DM9000_EPCR_ERPRW     (1<<1)  /* instruct to write */
-#define  DM9000_EPCR_ERPRR     (1<<2)  /* instruct to read */
-#define  DM9000_EPCR_EPOS_EEPROM (0<<3)        /* 1: PHY op, 0: EEPROM op */
-#define  DM9000_EPCR_EPOS_PHY    (1<<3)
-#define  DM9000_EPCR_WEP       (1<<4)
-#define  DM9000_EPCR_REEP      (1<<5)
-#define DM9000_EPAR            0x0C    /* 7:6 (!!) PHY id, 5:0 reg num */
-#define  DM9000_EPAR_EROA_MASK 0x3F    /* bits 0-5 */
+#define  DM9000_EPCR_ERPRW     (1<<1)  /* instruct to write, not SC */
+#define  DM9000_EPCR_ERPRR     (1<<2)  /* instruct to read, not SC */
+#define  DM9000_EPCR_EPOS_EEPROM (0<<3)        /* EEPROM operation */
+#define  DM9000_EPCR_EPOS_PHY    (1<<3)        /* PHY operation */
+#define  DM9000_EPCR_WEP       (1<<4)  /* EEPROM write enable */
+#define  DM9000_EPCR_REEP      (1<<5)  /* reload EEPROM contents, not SC */
+#define DM9000_EPAR            0x0C    /* EEPROM / PHY address */
+#define  DM9000_EPAR_EROA_MASK 0x3F    /* 7:6 (!!) PHY id, 5:0 addr/reg */
 #define  DM9000_EPAR_INT_PHY   0x40    /* EPAR[7:6] = 01 for internal PHY */
-#define DM9000_EPDRL           0x0D    /* data 7:0 */
-#define DM9000_EPDRH           0x0E    /* data 15:8 */
-#define DM9000_WCR             0x0F
+#define DM9000_EPDRL           0x0D    /* EEPROM / PHY data 7:0 */
+#define DM9000_EPDRH           0x0E    /* EEPROM / PHY data 15:8 */
+#define DM9000_WCR             0x0F    /* wakeup control and status */
+#define  DM9000_MAGIC          (1<<0)  /* magic frame arrived */
+#define  DM9000_SAMPLE         (1<<1)  /* sample frame arrived */
+#define  DM9000_LINK           (1<<2)  /* link change / status change found */
+#define  DM9000_MAGICEN                (1<<3)  /* enable magic frame event detect */
+#define  DM9000_SMAPLEEN       (1<<4)  /* enable sample frame event detect */
+#define  DM9000_LINKEN         (1<<5)  /* enable link change event detect */
 
 #define DM9000_PAB0            0x10    /* my station address 7:0 */
 #define DM9000_PAB1            0x11
@@ -135,46 +150,53 @@
 #define DM9000_MAB6            0x1C
 #define DM9000_MAB7            0x1D    /* 63:56, needs 0x80 to catch bcast */
 
-#define DM9000_GPCR            0x1E
-#define  DM9000_GPCR_GPIO0_OUT (1<<0)
-#define DM9000_GPR             0x1F
+#define DM9000_GPCR            0x1E    /* GPIO control */
+#define  DM9000_GPCR_GPIO0_OUT (1<<0)  /* bit-0 to control PHY */
+/* 3:0 select pin I/O direction (0001 def) */
+#define DM9000_GPR             0x1F    /* GPIO value to read / write */
 #define  DM9000_GPR_PHY_PWROFF (1<<0)  /* power down internal PHY */
-#define DM9000_TRPAL           0x22
-#define DM9000_TRPAH           0x23
-#define DM9000_RWPAL           0x24
-#define DM9000_RWPAH           0x25
+#define DM9000_TRPAL           0x22    /* Tx SRAM read pointer 7:0 */
+#define DM9000_TRPAH           0x23    /* Tx SRAM read pointer 15:8 */
+#define DM9000_RWPAL           0x24    /* Rx SRAM read pointer 7:0 */
+#define DM9000_RWPAH           0x25    /* Rx SRAM read pointer 15:8 */
 
+/* VID 0x0a46, PID 0x9000 */
 #define DM9000_VID0    0x28    /* vender ID 7:0 */
 #define DM9000_VID1    0x29    /* vender ID 15:8 */
 #define DM9000_PID0    0x2A    /* product ID 7:0 */
 #define DM9000_PID1    0x2B    /* product ID 15:8 */
+#define DM9000_CHIPR   0x2C    /* chip revision */
 
-#define DM9000_CHIPR   0x2C
-#define DM9000_SMCR    0x2F
+#define DM9000_SMCR    0x2F    /* "serial mode" control */
+#define  DM9000_FB0    (1<<0)  /* force shortest back-off time */
+#define  DM9000_FB1    (1<<1)  /* force longeset back-off time */
+#define  DM9000_FLC    (1<<2)  /* force late collsion */
+#define  DM9000_SM_EN  (1<<7)  /* serial mode enable */
 #define DM9000_MRCMDX  0xF0    /* "no increment"   read byte */
 #define DM9000_MRCMD   0xF2    /* "auto increment" read byte */
-#define DM9000_MRRL    0xF4
-#define DM9000_MRRH    0xF5
+#define DM9000_MRRL    0xF4    /* memory read address 7:0 */
+#define DM9000_MRRH    0xF5    /* memory read address 15:8 */
 #define DM9000_MWCMDX  0xF6    /* "no increment"   write byte */
 #define DM9000_MWCMD   0xF8    /* "auto increment" write byte */
-#define DM9000_MWRL    0xFA
-#define DM9000_MWRH    0xFB
+#define DM9000_MWRL    0xFA    /* memory write address 7:0 */
+#define DM9000_MWRH    0xFB    /* memory write address 15:8 */
 #define DM9000_TXPLL   0xFC    /* frame len 7:0 to transmit */
 #define DM9000_TXPLH   0xFD    /* frame len 15:8 to transmit */
 #define DM9000_ISR     0xFE    /* interrupt status report */
 #define  DM9000_IOMODE_MASK    0xC0
 #define  DM9000_IOMODE_SHIFT   6
-#define  DM9000_ISR_PRS                (1<<0)  /* receive completed */
-#define  DM9000_ISR_PTS                (1<<1)  /* transmit completed */
-#define  DM9000_ISR_ROS                (1<<2)
-#define  DM9000_ISR_ROOS       (1<<3)
+/* 7:6 I/O size (hard wired) 10b: 8-bit, 00b: 16-bit, 01b: 32-bit */
+#define  DM9000_ISR_PRS                (1<<0)  /* receive completed, W1C */
+#define  DM9000_ISR_PTS                (1<<1)  /* transmit completed, W1C */
+#define  DM9000_ISR_ROS                (1<<2)  /* Rx overflow latch, W1C */
+#define  DM9000_ISR_ROOS       (1<<3)  /* Rx overflow cntr overflowed, W1C */
 #define  DM9000_ISR_UNDERRUN   (1<<4)  /* Tx underrun detected */
 #define  DM9000_ISR_LNKCHNG    (1<<5)  /* link status change detected */
-#define DM9000_IMR     0xFF
-#define  DM9000_IMR_PRM        (1<<0)
-#define  DM9000_IMR_PTM        (1<<1)
-#define  DM9000_IMR_ROM        (1<<2)
-#define  DM9000_IMR_ROOM       (1<<3)
+#define DM9000_IMR     0xFF    /* interrupt mask */
+#define  DM9000_IMR_PRM        (1<<0)  /* enable receive event report */
+#define  DM9000_IMR_PTM        (1<<1)  /* enable xmit done event report */
+#define  DM9000_IMR_ROM        (1<<2)  /* enable Rx overflow event report */
+#define  DM9000_IMR_ROOM       (1<<3)  /* enable Rx overflow cntr ov report */
 #define  DM9000_IMR_PAR        (1<<7)  /* use 3/13K SRAM w/ auto wrap */
 
 #endif



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