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[src/trunk]: src/sys/dev/pci first step towards r5xx support:
details: https://anonhg.NetBSD.org/src/rev/993033a6f878
branches: trunk
changeset: 939719:993033a6f878
user: macallan <macallan%NetBSD.org@localhost>
date: Mon Sep 28 05:43:58 2020 +0000
description:
first step towards r5xx support:
- no CRTC programming yet, we just use whatever mode the (open)firmware hands
us
- palette control, fb location etc. all work
- hardware acceleration for character drawing, scrolling etc. works
- hardware cursor works
... tested & still works on various radeons in various macppc machines
diffstat:
sys/dev/pci/radeonfb.c | 620 +++++++++++++++++++++++++++++++--------------
sys/dev/pci/radeonfbvar.h | 7 +-
2 files changed, 425 insertions(+), 202 deletions(-)
diffs (truncated from 988 to 300 lines):
diff -r c1b56ffb8367 -r 993033a6f878 sys/dev/pci/radeonfb.c
--- a/sys/dev/pci/radeonfb.c Mon Sep 28 05:38:41 2020 +0000
+++ b/sys/dev/pci/radeonfb.c Mon Sep 28 05:43:58 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: radeonfb.c,v 1.109 2020/07/05 09:53:54 martin Exp $ */
+/* $NetBSD: radeonfb.c,v 1.110 2020/09/28 05:43:58 macallan Exp $ */
/*-
* Copyright (c) 2006 Itronix Inc.
@@ -70,7 +70,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.109 2020/07/05 09:53:54 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.110 2020/09/28 05:43:58 macallan Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -383,10 +383,10 @@
{ PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 },
{ PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 },
{ PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 },
+#endif
/* R5xx family */
- { 0x7240, RADEON_R420, 0 },
-#endif
+ { 0x7240, RADEON_R580, RFB_IS_AVIVO },
{ 0, 0, 0 }
};
@@ -426,6 +426,7 @@
{ RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}},
{ RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}},
{ RADEON_R420, {{-1, 0xb01cb}}},
+ { RADEON_R580, {{-1, 0xb01cb}}}, /* XXX likely bogus */
};
#define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */
@@ -514,6 +515,7 @@
case RADEON_R350:
case RADEON_RV380:
case RADEON_R420:
+ case RADEON_R580:
/* newer chips */
sc->sc_flags |= RFB_R300;
break;
@@ -587,12 +589,13 @@
PRINTREG(RADEON_TMDS_PLL_CNTL);
PRINTREG(RADEON_LVDS_GEN_CNTL);
PRINTREG(RADEON_DISP_HW_DEBUG);
- PRINTREG(RADEON_PIXCLKS_CNTL);
- PRINTREG(RADEON_CRTC_H_SYNC_STRT_WID);
- PRINTREG(RADEON_FP_H_SYNC_STRT_WID);
- PRINTREG(RADEON_CRTC2_H_SYNC_STRT_WID);
- PRINTREG(RADEON_FP_H2_SYNC_STRT_WID);
-
+ if (!IS_AVIVO(sc)) {
+ PRINTREG(RADEON_PIXCLKS_CNTL);
+ PRINTREG(RADEON_CRTC_H_SYNC_STRT_WID);
+ PRINTREG(RADEON_FP_H_SYNC_STRT_WID);
+ PRINTREG(RADEON_CRTC2_H_SYNC_STRT_WID);
+ PRINTREG(RADEON_FP_H2_SYNC_STRT_WID);
+ }
/*
* XXX
* This was if (IS_RV100()), which is set for all pre-R3xx chips.
@@ -883,12 +886,11 @@
/* N.B.: radeon wants 64-byte aligned stride */
dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8;
dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN);
- DPRINTF(("stride: %d %d\n", dp->rd_stride, dp->rd_virtx));
dp->rd_offset = sc->sc_fboffset * i;
dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt,
sc->sc_memh) + dp->rd_offset;
- dp->rd_curoff = sc->sc_fboffset - 4096; /* 4KB cursor space */
+ dp->rd_curoff = sc->sc_fboffset - 16384; /* 16KB cursor space */
dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff;
DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr));
@@ -905,10 +907,11 @@
dp->rd_bpp);
goto error;
}
-
DPRINTF(("init engine\n"));
/* XXX: this seems suspicious - per display engine
initialization? */
+
+ radeonfb_modeswitch(dp);
radeonfb_engine_init(dp);
/* copy the template into place */
@@ -980,7 +983,6 @@
if (dp->rd_console) {
- radeonfb_modeswitch(dp);
wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0,
defattr);
#ifdef SPLASHSCREEN
@@ -1000,7 +1002,6 @@
*/
memset(ri->ri_bits, 0, 1024);
- radeonfb_modeswitch(dp);
#ifdef SPLASHSCREEN
if (splash_render(&dp->rd_splash,
SPLASH_F_CENTER|SPLASH_F_FILL) == 0)
@@ -1021,23 +1022,27 @@
callout_init(&dp->rd_bl_lvds_co, 0);
callout_setfunc(&dp->rd_bl_lvds_co,
radeonfb_lvds_callout, dp);
+
dp->rd_bl_on = 1;
if (sc->sc_flags & RFB_MOB) {
dp->rd_bl_level = radeonfb_get_backlight(dp);
} else
dp->rd_bl_level = 128;
+
radeonfb_set_backlight(dp, dp->rd_bl_level);
}
-
for (i = 0; i < RADEON_NDISPLAYS; i++)
radeonfb_init_palette(&sc->sc_displays[i]);
-
- if (HAS_CRTC2(sc)) {
+
+ if (HAS_CRTC2(sc) && !IS_AVIVO(sc)) {
CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS);
}
- CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS);
- SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON);
+ if (!IS_AVIVO(sc)) {
+ CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS);
+ SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON);
+ }
+
pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP,
radeonfb_brightness_up, TRUE);
pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN,
@@ -1052,18 +1057,19 @@
(config_found_ia(dev, "drm", aux, radeonfb_drm_print) != 0);
DPRINTF(("needs_unmap: %d\n", sc->sc_needs_unmap));
- PRINTREG(RADEON_CRTC_EXT_CNTL);
- PRINTREG(RADEON_CRTC_GEN_CNTL);
- PRINTREG(RADEON_CRTC2_GEN_CNTL);
- PRINTREG(RADEON_DISP_OUTPUT_CNTL);
- PRINTREG(RADEON_DAC_CNTL2);
- PRINTREG(RADEON_FP_GEN_CNTL);
- PRINTREG(RADEON_FP2_GEN_CNTL);
- PRINTREG(RADEON_TMDS_CNTL);
- PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL);
- PRINTREG(RADEON_TMDS_PLL_CNTL);
- PRINTREG(RADEON_PIXCLKS_CNTL);
-
+ if (!IS_AVIVO(sc)) {
+ PRINTREG(RADEON_CRTC_EXT_CNTL);
+ PRINTREG(RADEON_CRTC_GEN_CNTL);
+ PRINTREG(RADEON_CRTC2_GEN_CNTL);
+ PRINTREG(RADEON_DISP_OUTPUT_CNTL);
+ PRINTREG(RADEON_DAC_CNTL2);
+ PRINTREG(RADEON_FP_GEN_CNTL);
+ PRINTREG(RADEON_FP2_GEN_CNTL);
+ PRINTREG(RADEON_TMDS_CNTL);
+ PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL);
+ PRINTREG(RADEON_TMDS_PLL_CNTL);
+ PRINTREG(RADEON_PIXCLKS_CNTL);
+ }
return;
error:
@@ -1173,10 +1179,12 @@
return 0;
case WSDISPLAYIO_SVIDEO:
- radeonfb_blank(dp,
- (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF));
- radeonfb_switch_backlight(dp,
- (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON));
+ if (dp->rd_wsmode != WSDISPLAYIO_MODE_MAPPED) {
+ radeonfb_blank(dp,
+ (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF));
+ radeonfb_switch_backlight(dp,
+ (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON));
+ }
pmf_event_inject(NULL,
(*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON) ?
PMFE_DISPLAY_ON : PMFE_DISPLAY_OFF);
@@ -2268,8 +2276,27 @@
struct radeonfb_softc *sc = dp->rd_softc;
int i;
+ if (IS_AVIVO(sc)) {
+ /*
+ * no actual mode setting yet, we just make sure the CRTCs
+ * point at the right memory ranges and use the same pitch
+ * for the drawing engine
+ */
+ if (GET32(sc, AVIVO_D1CRTC_CONTROL) & AVIVO_CRTC_EN) {
+ CLR32(sc, AVIVO_D1GRPH_CONTROL, AVIVO_D1GRPH_MACRO_ADDRESS_MODE);
+ dp->rd_stride = GET32(sc, AVIVO_D1GRPH_PITCH);
+ PUT32(sc, AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, 0);
+ }
+ if (GET32(sc, AVIVO_D2CRTC_CONTROL) & AVIVO_CRTC_EN) {
+ CLR32(sc, AVIVO_D2GRPH_CONTROL, AVIVO_D1GRPH_MACRO_ADDRESS_MODE);
+ dp->rd_stride = GET32(sc, AVIVO_D2GRPH_PITCH);
+ PUT32(sc, AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, 0);
+ }
+ return;
+ }
+
/* blank the display while we switch modes */
- radeonfb_blank(dp, 1);
+ //radeonfb_blank(dp, 1);
#if 0
SET32(sc, RADEON_CRTC_EXT_CNTL,
@@ -2288,11 +2315,6 @@
PUT32(sc, RADEON_GEN_INT_CNTL, 0);
PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0);
PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0);
- /*
- * Apple OF hands us R3xx radeons with tiling enabled - explicitly
- * disable it here
- */
- PUT32(sc, RADEON_SURFACE_CNTL, RADEON_SURF_TRANSLATION_DIS);
for (i = 0; i < dp->rd_ncrtcs; i++)
radeonfb_setcrtc(dp, i);
@@ -2323,7 +2345,7 @@
struct videomode *mode;
struct radeonfb_softc *sc;
struct radeonfb_crtc *cp;
- uint32_t v;
+ uint32_t v, hd, vd;
uint32_t gencntl;
uint32_t htotaldisp;
uint32_t hsyncstrt;
@@ -2425,57 +2447,65 @@
PUT32(sc, RADEON_CRTC_EXT_CNTL, v);
PRINTREG(RADEON_CRTC_EXT_CNTL);
- /*
- * H_TOTAL_DISP
- */
- v = ((mode->hdisplay / 8) - 1) << 16;
- v |= (mode->htotal / 8) - 1;
- PUT32(sc, htotaldisp, v);
- DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
- if (fphtotaldisp) {
- PUT32(sc, fphtotaldisp, v);
- DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
- }
- /*
- * H_SYNC_STRT_WID
- */
- v = (((mode->hsync_end - mode->hsync_start) / 8) << 16);
- v |= (mode->hsync_start - 8); /* match xf86-video-radeon */
- if (mode->flags & VID_NHSYNC)
- v |= RADEON_CRTC_H_SYNC_POL;
- PUT32(sc, hsyncstrt, v);
- DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
- if (fphsyncstrt) {
- PUT32(sc, fphsyncstrt, v);
- DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
+ hd = ((GET32(sc, htotaldisp) >> 16) + 1) * 8;
+ vd = (GET32(sc, vtotaldisp) >> 16) + 1;
+ DPRINTF(("res %d x %d\n", hd, vd));
+
+ if ((hd != mode->hdisplay) || (vd != mode->vdisplay)) {
+
+ /*
+ * H_TOTAL_DISP
+ */
+ v = ((mode->hdisplay / 8) - 1) << 16;
+ v |= (mode->htotal / 8) - 1;
+ PRINTREG(RADEON_CRTC_H_TOTAL_DISP);
+ PUT32(sc, htotaldisp, v);
+ DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
+ if (fphtotaldisp) {
+ PRINTREG(RADEON_FP_CRTC_H_TOTAL_DISP);
+ PUT32(sc, fphtotaldisp, v);
+ DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
+ }
+ /*
+ * H_SYNC_STRT_WID
+ */
+ v = (((mode->hsync_end - mode->hsync_start) / 8) << 16);
+ v |= (mode->hsync_start - 8); /* match xf86-video-radeon */
+ if (mode->flags & VID_NHSYNC)
+ v |= RADEON_CRTC_H_SYNC_POL;
+ PUT32(sc, hsyncstrt, v);
+ DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
+ if (fphsyncstrt) {
+ PUT32(sc, fphsyncstrt, v);
+ DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
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