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[src/nathanw_sa]: src/sys/arch/hpcmips/dev Add MQ200_USECRT option, which ena...
details: https://anonhg.NetBSD.org/src/rev/e0d65e3efdc6
branches: nathanw_sa
changeset: 504593:e0d65e3efdc6
user: takemura <takemura%NetBSD.org@localhost>
date: Sun Mar 25 13:06:54 2001 +0000
description:
Add MQ200_USECRT option, which enables CRT output on MC/R530.
This is kernel configuration option and you can't enable and disable CRT
dynamically for now.
diffstat:
sys/arch/hpcmips/dev/mq200debug.c | 547 ++++++++++++++++++++++++++++++++++++
sys/arch/hpcmips/dev/mq200machdep.c | 233 +++++++++++++++
sys/arch/hpcmips/dev/mq200priv.h | 156 ++++++++++
3 files changed, 936 insertions(+), 0 deletions(-)
diffs (truncated from 948 to 300 lines):
diff -r 5e8e5a96ea56 -r e0d65e3efdc6 sys/arch/hpcmips/dev/mq200debug.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/hpcmips/dev/mq200debug.c Sun Mar 25 13:06:54 2001 +0000
@@ -0,0 +1,547 @@
+/* $NetBSD: mq200debug.c,v 1.1.12.2 2001/03/25 13:06:54 takemura Exp $ */
+
+/*-
+ * Copyright (c) 2001 TAKEMURA Shin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#ifdef _KERNEL
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#else
+#include <stdio.h>
+#endif
+#include <sys/types.h>
+
+#include <machine/platid.h>
+#include <machine/platid_mask.h>
+
+#include "opt_mq200.h"
+#include "mq200var.h"
+#include "mq200reg.h"
+#include "mq200priv.h"
+
+#define ENABLE(b) ((b)?"enable":"disable")
+
+#ifdef MQ200_DEBUG
+
+char *mq200_clknames[] = { "BUS", "PLL1", "PLL2", "PLL3" };
+
+void
+mq200_dump_pll(struct mq200_softc *sc)
+{
+ int n, m;
+ u_int32_t reg, pm00r;
+ int clocks[4];
+ int memclock, geclock;
+ static char *clknames[] = { "BUS", "PLL1", "PLL2", "PLL3" };
+ static char *fd_names[] = { "1", "1.5", "2.5", "3.5", "4.5", "5.5", "6.5" };
+ static int fd_vals[] = { 10, 15, 25, 35, 45, 55, 65 };
+#define FIXEDFLOAT1000(a) (a)/1000, (a)%1000
+
+ /* PM00R */
+ pm00r = mq200_read(sc, MQ200_PMCR);
+ geclock = (pm00r&MQ200_PMC_GE_CLK_MASK)>>MQ200_PMC_GE_CLK_SHIFT;
+
+ /* MM01R */
+ reg = mq200_read(sc, MQ200_MMR(1));
+ memclock = (reg & MQ200_MM01_CLK_PLL2) ? 2 : 1;
+
+ /* bus clock */
+ clocks[0] = 0;
+
+ /* PLL1 */
+ reg = mq200_read(sc, MQ200_DCMISCR);
+ m = ((reg & MQ200_PLL_M_MASK) >> MQ200_PLL_M_SHIFT) + 1;
+ n = ((((reg & MQ200_PLL_N_MASK) >> MQ200_PLL_N_SHIFT) + 1) |
+ ((pm00r & MQ200_PMC_PLL1_N) << MQ200_PMC_PLL1_N_SHIFT));
+ n <<= ((reg & MQ200_PLL_P_MASK) >> MQ200_PLL_P_SHIFT);
+ printf(" PLL1:%3d.%03dMHz(0x%08x, %d.%03dMHzx%3d/%3d)\n",
+ FIXEDFLOAT1000(sc->sc_baseclock*m/n),
+ reg, FIXEDFLOAT1000(sc->sc_baseclock), m, n);
+ clocks[1] = sc->sc_baseclock*m/n;
+
+ /* PLL2 */
+ if (pm00r & MQ200_PMC_PLL2_ENABLE) {
+ reg = mq200_read(sc, MQ200_PLL2R);
+ m = ((reg & MQ200_PLL_M_MASK) >> MQ200_PLL_M_SHIFT) + 1;
+ n = ((((reg & MQ200_PLL_N_MASK) >> MQ200_PLL_N_SHIFT) +1) <<
+ ((reg & MQ200_PLL_P_MASK) >> MQ200_PLL_P_SHIFT));
+ clocks[2] = sc->sc_baseclock*m/n;
+ printf(" PLL2:%3d.%03dMHz(0x%08x, %d.%03dMHzx%3d/%3d)\n",
+ FIXEDFLOAT1000(sc->sc_baseclock*m/n),
+ reg, FIXEDFLOAT1000(sc->sc_baseclock), m, n);
+ } else {
+ printf(" PLL2: disable\n");
+ clocks[2] = 0;
+ }
+
+ /* PLL3 */
+ if (pm00r & MQ200_PMC_PLL3_ENABLE) {
+ reg = mq200_read(sc, MQ200_PLL3R);
+ m = (((reg & MQ200_PLL_M_MASK) >> MQ200_PLL_M_SHIFT) + 1);
+ n = ((((reg & MQ200_PLL_N_MASK) >> MQ200_PLL_N_SHIFT) + 1) <<
+ ((reg & MQ200_PLL_P_MASK) >> MQ200_PLL_P_SHIFT));
+ clocks[3] = sc->sc_baseclock*m/n;
+ printf(" PLL3:%3d.%03dMHz(0x%08x, %d.%03dMHzx%3d/%3d)\n",
+ FIXEDFLOAT1000(sc->sc_baseclock*m/n),
+ reg, FIXEDFLOAT1000(sc->sc_baseclock), m, n);
+ } else {
+ printf(" PLL3: disable\n");
+ clocks[3] = 0;
+ }
+
+ printf(" MEM:%3d.%03dMHz(%s)\n",
+ FIXEDFLOAT1000(clocks[memclock]),
+ clknames[memclock]);
+ printf(" GE:%3d.%03dMHz(%s)\n",
+ FIXEDFLOAT1000(clocks[geclock]),
+ clknames[geclock]);
+
+ /* GC1 */
+ reg = mq200_read(sc, MQ200_GCCR(MQ200_GC1));
+ if (reg & MQ200_GCC_ENABLE) {
+ int fd, sd, rc;
+ rc = (reg&MQ200_GCC_RCLK_MASK)>>MQ200_GCC_RCLK_SHIFT;
+ fd = (reg&MQ200_GCC_MCLK_FD_MASK)>>MQ200_GCC_MCLK_FD_SHIFT;
+ sd = (reg&MQ200_GCC_MCLK_SD_MASK)>>MQ200_GCC_MCLK_SD_SHIFT;
+ printf(" GC1:%3d.%03dMHz(%s/%s/%d)",
+ FIXEDFLOAT1000(clocks[rc]*10/fd_vals[fd]/sd),
+ clknames[rc], fd_names[fd], sd);
+ /* GC01R */
+ reg = mq200_read(sc, MQ200_GC1CRTCR);
+ if (reg&MQ200_GC1CRTC_DACEN)
+ printf(", CRT");
+ reg = mq200_read(sc, MQ200_FPCR);
+ if ((reg & MQ200_FPC_ENABLE) && !(reg & MQ200_FPC_GC2))
+ printf(", LCD");
+ printf("\n");
+ } else {
+ printf(" GC1: disable\n");
+ }
+
+ /* GC2 */
+ reg = mq200_read(sc, MQ200_GCCR(MQ200_GC2));
+ if (reg & MQ200_GCC_ENABLE) {
+ int fd, sd, rc;
+ rc = (reg&MQ200_GCC_RCLK_MASK)>>MQ200_GCC_RCLK_SHIFT;
+ fd = (reg&MQ200_GCC_MCLK_FD_MASK)>>MQ200_GCC_MCLK_FD_SHIFT;
+ sd = (reg&MQ200_GCC_MCLK_SD_MASK)>>MQ200_GCC_MCLK_SD_SHIFT;
+ printf(" GC2:%3d.%03dMHz(%s/%s/%d)",
+ FIXEDFLOAT1000(clocks[rc]*10/fd_vals[fd]/sd),
+ clknames[rc], fd_names[fd], sd);
+ reg = mq200_read(sc, MQ200_FPCR);
+ if ((reg & MQ200_FPC_ENABLE) && (reg & MQ200_FPC_GC2))
+ printf(", FP");
+ printf("\n");
+ } else {
+ printf(" GC2: disable\n");
+ }
+}
+
+struct {
+ char *name;
+ u_int32_t base;
+ int start, end;
+} regs[] = {
+ { "GC", MQ200_GCR(0), 0x00, 0x13 },
+ { "GC", MQ200_GCR(0), 0x20, 0x33 },
+ { "FP", MQ200_FP, 0x00, 0x0f },
+ { "CC", MQ200_CC, 0x00, 0x01 },
+ { "PC", MQ200_PC, 0x00, 0x05 },
+ { "MM", MQ200_MM, 0x00, 0x04 },
+ { "DC", MQ200_DC, 0x00, 0x03 },
+ { "PM", MQ200_PM, 0x00, 0x03 },
+ { "PM", MQ200_PM, 0x06, 0x07 },
+ { "IN", MQ200_IN, 0x00, 0x03 },
+};
+
+char *
+mq200_regname(struct mq200_softc *sc, int offset, char *buf, int bufsize)
+{
+ int i;
+
+ for (i = 0; i < sizeof(regs)/sizeof(*regs); i++)
+ if (regs[i].base + regs[i].start * 4 <= offset &&
+ offset <= regs[i].base + regs[i].end * 4) {
+ sprintf(buf, "%s%02XR", regs[i].name,
+ (offset - regs[i].base) / 4);
+ return (buf);
+ }
+ sprintf(buf, "OFFSET %02X", offset);
+ return (buf);
+}
+
+void
+mq200_dump_all(struct mq200_softc *sc)
+{
+ int i, j;
+
+ for (i = 0; i < sizeof(regs)/sizeof(*regs); i++)
+ for (j = regs[i].start; j <= regs[i].end; j++)
+ printf("%s%02XR: %08x\n",
+ regs[i].name, j,
+ mq200_read(sc, regs[i].base + (j * 4)));
+}
+
+void
+mq200_write(struct mq200_softc *sc, int offset, u_int32_t data)
+{
+ int i;
+ char buf[32];
+
+ for (i = 0; i < MQ200_I_MAX; i++) {
+ if (sc->sc_regctxs[i].offset == offset)
+ printf("mq200_write: WARNING: raw access %s\n",
+ mq200_regname(sc, offset, buf, sizeof(buf)));
+ }
+
+ mq200_writex(sc, offset, data);
+}
+
+#if 0
+void
+mq200_dump_gc(struct mq200_softc *sc, int gc)
+{
+ u_int32_t reg;
+ char *depth_names[] = {
+ "1bpp with CLUT",
+ "2bpp with CLUT",
+ "4bpp with CLUT",
+ "8bpp with CLUT",
+ "16bpp with CLUT",
+ "24bpp with CLUT",
+ "32bpp(RGB) with CLUT",
+ "32bpp(BGR) with CLUT",
+ "1bpp w/o CLUT",
+ "2bpp w/o CLUT",
+ "4bpp w/o CLUT",
+ "8bpp w/o CLUT",
+ "16bpp w/o CLUT",
+ "24bpp w/o CLUT",
+ "32bpp(RGB) w/o CLUT",
+ "32bpp(BGR) w/o CLUT",
+ };
+ char *rc_names[] = { "BUS", "PLL1", "PLL2", "PLL3" };
+ char *fd_names[] = { "1", "1.5", "2.5", "3.5", "4.5", "5.5", "6.5" };
+
+ /*
+ * GC00R Graphics Controller Control
+ */
+ reg = mq200_read(sc, MQ200_GCCR(gc));
+ printf("GC00R=0x%08x: ", reg);
+ printf("%s %s%s%s%s%s\n",
+ ENABLE(reg & MQ200_GCC_ENABLE),
+ (reg & MQ200_GCC_HCRESET)?"HC_reset ":"",
+ (reg & MQ200_GCC_VCRESET)?"VC_reset ":"",
+ (reg & MQ200_GCC_HCEN)?"cursor_enable ":"",
+ (reg & MQ200_GCC_TESTMODE0)?"test_mode0 ":"",
+ (reg & MQ200_GCC_TESTMODE1)?"test_mode1 ":"");
+ printf(" window: %s %s\n",
+ ENABLE(reg & MQ200_GCC_WINEN),
+ depth_names[(reg&MQ200_GCC_DEPTH_MASK)>>MQ200_GCC_DEPTH_SHIFT]);
+ printf(" altwin: %s %s\n",
+ ENABLE(reg & MQ200_GCC_ALTEN),
+ depth_names[(reg&MQ200_GCC_ALTDEPTH_MASK)>>MQ200_GCC_ALTDEPTH_SHIFT]);
+ printf(" clock: root_clock/first_div/second_div = %s/%s/%d\n",
+ rc_names[(reg&MQ200_GCC_RCLK_MASK)>>MQ200_GCC_RCLK_SHIFT],
+ fd_names[(reg&MQ200_GCC_MCLK_FD_MASK)>>MQ200_GCC_MCLK_FD_SHIFT],
+ (reg&MQ200_GCC_MCLK_SD_MASK)>>MQ200_GCC_MCLK_SD_SHIFT);
+
+ if (gc == 0) {
+ /*
+ * GC01R Graphics Controller CRT Control
+ */
+ reg = mq200_read(sc, MQ200_GC1CRTCR);
+ printf("GC01R=0x%08x:\n", reg);
+ printf(" CRT DAC: %s\n",
+ ENABLE(reg&MQ200_GC1CRTC_DACEN));
+
+ printf(" power down mode: H-sync=");
+ switch (reg & MQ200_GC1CRTC_HSYNC_PMMASK) {
+ case MQ200_GC1CRTC_HSYNC_PMNORMAL:
+ if (reg & MQ200_GC1CRTC_HSYNC_PMCLK)
+ printf("PMCLK");
+ else
+ printf("LOW");
+ break;
+ case MQ200_GC1CRTC_HSYNC_PMLOW:
+ printf("LOW");
+ break;
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