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[src/trunk]: src/sys/arch/sparc/dev * Remove MAX_DMA_LEN & si_minphys().
details: https://anonhg.NetBSD.org/src/rev/ff60107a7e9d
branches: trunk
changeset: 494206:ff60107a7e9d
user: pk <pk%NetBSD.org@localhost>
date: Mon Jul 03 20:55:12 2000 +0000
description:
* Remove MAX_DMA_LEN & si_minphys().
* Disable the DMA engine when setting up a DMA transfer, just in case
the 5380 driver didn't instruct us to do so already.
* More useful debug output when entering the "left-over bytes" case after
a DMA transfer finishes.
diffstat:
sys/arch/sparc/dev/si.c | 72 +++++++++++++++++-------------------------------
1 files changed, 26 insertions(+), 46 deletions(-)
diffs (181 lines):
diff -r 1511f93a0bd5 -r ff60107a7e9d sys/arch/sparc/dev/si.c
--- a/sys/arch/sparc/dev/si.c Mon Jul 03 20:12:42 2000 +0000
+++ b/sys/arch/sparc/dev/si.c Mon Jul 03 20:55:12 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: si.c,v 1.64 2000/06/29 14:06:40 pk Exp $ */
+/* $NetBSD: si.c,v 1.65 2000/07/03 20:55:12 pk Exp $ */
/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
@@ -132,14 +132,6 @@
*/
#define MIN_DMA_LEN 128
-/*
- * Transfers lager than 65535 bytes need to be split-up.
- * (Some of the FIFO logic has only 16 bits counters.)
- * Make the size an integer multiple of the page size
- * to avoid buf/cluster remap problems. (paranoid?)
- */
-#define MAX_DMA_LEN 0xE000
-
#ifdef DEBUG
int si_debug = 0;
static int si_link_flags = 0 /* | SDEV_DB2 */ ;
@@ -189,13 +181,12 @@
#define SI_DO_RESELECT 0x04 /* Allow disconnect/reselect */
#define SI_OPTIONS_MASK (SI_ENABLE_DMA|SI_DMA_INTR|SI_DO_RESELECT)
#define SI_OPTIONS_BITS "\10\3RESELECT\2DMA_INTR\1DMA"
-int si_options = SI_ENABLE_DMA|SI_DMA_INTR;
+int si_options = SI_ENABLE_DMA|SI_DMA_INTR|SI_DO_RESELECT;
static int si_match __P((struct device *, struct cfdata *, void *));
static void si_attach __P((struct device *, struct device *, void *));
static int si_intr __P((void *));
static void si_reset_adapter __P((struct ncr5380_softc *));
-static void si_minphys __P((struct buf *));
void si_dma_alloc __P((struct ncr5380_softc *));
void si_dma_free __P((struct ncr5380_softc *));
@@ -371,7 +362,7 @@
#endif
ncr_sc->sc_link.scsipi_scsi.adapter_target = 7;
- ncr_sc->sc_adapter.scsipi_minphys = si_minphys;
+ ncr_sc->sc_adapter.scsipi_minphys = minphys;
/*
* Initialize si board itself.
@@ -389,21 +380,6 @@
}
}
-static void
-si_minphys(struct buf *bp)
-{
- if (bp->b_bcount > MAX_DMA_LEN) {
-#ifdef DEBUG
- if (si_debug) {
- printf("si_minphys len = 0x%x.\n", MAX_DMA_LEN);
- Debugger();
- }
-#endif
- bp->b_bcount = MAX_DMA_LEN;
- }
- return (minphys(bp));
-}
-
#define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \
SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR )
@@ -739,7 +715,7 @@
struct si_softc *sc = (struct si_softc *)ncr_sc;
struct sci_req *sr = ncr_sc->sc_current;
struct si_dma_handle *dh = sr->sr_dma_hand;
- u_long data_pa;
+ u_long dva;
int xlen;
u_int mode;
u_int16_t csr;
@@ -747,17 +723,17 @@
/*
* Get the DVMA mapping for this segment.
*/
- data_pa = (u_long)(dh->dh_dvma);
- if (data_pa & 1)
- panic("si_dma_start: bad pa=0x%lx", data_pa);
+ dva = (u_long)(dh->dh_dvma);
+ if (dva & 1)
+ panic("si_dma_start: bad dmaaddr=0x%lx", dva);
xlen = ncr_sc->sc_datalen;
xlen &= ~1;
sc->sc_xlen = xlen; /* XXX: or less... */
#ifdef DEBUG
if (si_debug & 2) {
- printf("si_dma_start: dh=%p, pa=0x%lx, xlen=%d\n",
- dh, data_pa, xlen);
+ printf("si_dma_start: dh=%p, dmaaddr=0x%lx, xlen=%d\n",
+ dh, dva, xlen);
}
#endif
@@ -765,7 +741,13 @@
* Set up the DMA controller.
* Note that (dh->dh_len < sc_datalen)
*/
+
csr = SIREG_READ(ncr_sc, SIREG_CSR);
+
+ /* Disable DMA while we're setting up the transfer */
+ csr &= ~SI_CSR_DMA_EN;
+
+ /* Reset FIFO (again?) */
csr &= ~SI_CSR_FIFO_RES; /* active low */
SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
csr |= SI_CSR_FIFO_RES;
@@ -779,24 +761,19 @@
}
SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
- if (data_pa & 2) {
+ if (dva & 2) {
csr |= SI_CSR_BPCON;
} else {
csr &= ~SI_CSR_BPCON;
}
SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
- SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRH, (u_int16_t)(data_pa >> 16));
- SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRL, (u_int16_t)(data_pa & 0xFFFF));
-
+ SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRH, (u_int16_t)(dva >> 16));
+ SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRL, (u_int16_t)(dva & 0xFFFF));
SIREG_WRITE(ncr_sc, SIREG_DMA_CNTH, (u_int16_t)(xlen >> 16));
SIREG_WRITE(ncr_sc, SIREG_DMA_CNTL, (u_int16_t)(xlen & 0xFFFF));
-
-#if 1
- /* Set it anyway, even though dma_count hits it? */
SIREG_WRITE(ncr_sc, SIREG_FIFO_CNTH, (u_int16_t)(xlen >> 16));
SIREG_WRITE(ncr_sc, SIREG_FIFO_CNT, (u_int16_t)(xlen & 0xFFFF));
-#endif
/*
* Acknowledge the phase change. (After DMA setup!)
@@ -824,7 +801,7 @@
NCR5380_WRITE(ncr_sc, sci_irecv, 0); /* start it */
}
- /* Let'er rip! */
+ /* Enable DMA engine */
csr |= SI_CSR_DMA_EN;
SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
@@ -870,7 +847,7 @@
csr = SIREG_READ(ncr_sc, SIREG_CSR);
/* First, halt the DMA engine. */
- csr &= ~SI_CSR_DMA_EN; /* VME only */
+ csr &= ~SI_CSR_DMA_EN;
SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
if (csr & (SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)) {
@@ -933,12 +910,15 @@
{
char *cp = ncr_sc->sc_dataptr;
u_int16_t bprh, bprl;
-#ifdef DEBUG
- printf("si: Got Left-over bytes!\n");
-#endif
+
bprh = SIREG_READ(ncr_sc, SIREG_BPRH);
bprl = SIREG_READ(ncr_sc, SIREG_BPRL);
+#ifdef DEBUG
+ printf("si: got left-over bytes: bprh=%x, bprl=%x, csr=%x\n",
+ bprh, bprl, csr);
+#endif
+
if (csr & SI_CSR_BPCON) {
/* have SI_CSR_BPCON */
cp[-1] = (bprl & 0xff00) >> 8;
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