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[src/trunk]: src/sys/arch/sgimips Prepend HPC3 macros universally with "HPC3_...
details: https://anonhg.NetBSD.org/src/rev/c50489e1b756
branches: trunk
changeset: 572357:c50489e1b756
user: rumble <rumble%NetBSD.org@localhost>
date: Thu Dec 30 23:18:09 2004 +0000
description:
Prepend HPC3 macros universally with "HPC3_" to distinctly recognise
the corresponding revision and maintain consistency with HPC1.
No functional change intended.
diffstat:
sys/arch/sgimips/hpc/haltwo.c | 46 ++--
sys/arch/sgimips/hpc/hpc.c | 130 +++++-----
sys/arch/sgimips/hpc/hpcdma.c | 6 +-
sys/arch/sgimips/hpc/hpcreg.h | 421 ++++++++++++++++++------------------
sys/arch/sgimips/hpc/if_sq.c | 69 +++--
sys/arch/sgimips/hpc/sqvar.h | 8 +-
sys/arch/sgimips/sgimips/console.c | 6 +-
7 files changed, 348 insertions(+), 338 deletions(-)
diffs (truncated from 1112 to 300 lines):
diff -r 16cd5cc0c6d3 -r c50489e1b756 sys/arch/sgimips/hpc/haltwo.c
--- a/sys/arch/sgimips/hpc/haltwo.c Thu Dec 30 23:03:19 2004 +0000
+++ b/sys/arch/sgimips/hpc/haltwo.c Thu Dec 30 23:18:09 2004 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: haltwo.c,v 1.4 2004/10/29 12:57:16 yamt Exp $ */
+/* $NetBSD: haltwo.c,v 1.5 2004/12/30 23:18:09 rumble Exp $ */
/*
* Copyright (c) 2003 Ilpo Ruotsalainen
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: haltwo.c,v 1.4 2004/10/29 12:57:16 yamt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: haltwo.c,v 1.5 2004/12/30 23:18:09 rumble Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -233,7 +233,7 @@
if (next_intr == segp->ds_len) {
/* Generate intr after this DMA buffer */
- descp->hpc3_hdd_ctl |= HDD_CTL_INTR;
+ descp->hpc3_hdd_ctl |= HPC3_HDD_CTL_INTR;
next_intr = blksize;
} else
next_intr -= segp->ds_len;
@@ -278,19 +278,19 @@
sc->sc_dma_tag = haa->ha_dmat;
if (bus_space_subregion(haa->ha_st, haa->ha_sh, haa->ha_devoff,
- HPC_PBUS_CH0_DEVREGS_SIZE, &sc->sc_ctl_sh)) {
+ HPC3_PBUS_CH0_DEVREGS_SIZE, &sc->sc_ctl_sh)) {
aprint_error(": unable to map control registers\n");
return;
}
- if (bus_space_subregion(haa->ha_st, haa->ha_sh, HPC_PBUS_CH2_DEVREGS,
- HPC_PBUS_CH2_DEVREGS_SIZE, &sc->sc_vol_sh)) {
+ if (bus_space_subregion(haa->ha_st, haa->ha_sh, HPC3_PBUS_CH2_DEVREGS,
+ HPC3_PBUS_CH2_DEVREGS_SIZE, &sc->sc_vol_sh)) {
aprint_error(": unable to map volume registers\n");
return;
}
if (bus_space_subregion(haa->ha_st, haa->ha_sh, haa->ha_dmaoff,
- HPC_PBUS_DMAREGS_SIZE, &sc->sc_dma_sh)) {
+ HPC3_PBUS_DMAREGS_SIZE, &sc->sc_dma_sh)) {
aprint_error(": unable to map DMA registers\n");
return;
}
@@ -327,9 +327,9 @@
}
/* XXX Magic PBUS CFGDMA values from Linux HAL2 driver XXX */
- bus_space_write_4(haa->ha_st, haa->ha_sh, HPC_PBUS_CH0_CFGDMA,
+ bus_space_write_4(haa->ha_st, haa->ha_sh, HPC3_PBUS_CH0_CFGDMA,
0x8208844);
- bus_space_write_4(haa->ha_st, haa->ha_sh, HPC_PBUS_CH1_CFGDMA,
+ bus_space_write_4(haa->ha_st, haa->ha_sh, HPC3_PBUS_CH1_CFGDMA,
0x8208844);
/* Unmute output */
@@ -350,8 +350,8 @@
struct haltwo_softc *sc = v;
int ret = 0;
- if (bus_space_read_4(sc->sc_st, sc->sc_dma_sh, HPC_PBUS_CH0_CTL)
- & HPC_PBUS_DMACTL_IRQ) {
+ if (bus_space_read_4(sc->sc_st, sc->sc_dma_sh, HPC3_PBUS_CH0_CTL)
+ & HPC3_PBUS_DMACTL_IRQ) {
sc->sc_dac.intr(sc->sc_dac.intr_arg);
ret = 1;
@@ -501,8 +501,8 @@
struct haltwo_softc *sc = v;
/* Disable PBUS DMA */
- bus_space_write_4(sc->sc_st, sc->sc_dma_sh, HPC_PBUS_CH0_CTL,
- HPC_PBUS_DMACTL_ACT_LD);
+ bus_space_write_4(sc->sc_st, sc->sc_dma_sh, HPC3_PBUS_CH0_CTL,
+ HPC3_PBUS_DMACTL_ACT_LD);
return (0);
}
@@ -731,8 +731,8 @@
}
/* Disable PBUS DMA */
- bus_space_write_4(sc->sc_st, sc->sc_dma_sh, HPC_PBUS_CH0_CTL,
- HPC_PBUS_DMACTL_ACT_LD);
+ bus_space_write_4(sc->sc_st, sc->sc_dma_sh, HPC3_PBUS_CH0_CTL,
+ HPC3_PBUS_DMACTL_ACT_LD);
/* Disable HAL2 codec DMA */
haltwo_read_indirect(sc, HAL2_IREG_DMA_PORT_EN, &tmp, NULL);
@@ -750,20 +750,20 @@
" fifobeg = %d fifoend = %d\n", param->hw_channels, highwater,
fifobeg, fifoend));
- ctrl = HPC_PBUS_DMACTL_RT
- | HPC_PBUS_DMACTL_ACT_LD
- | (highwater << HPC_PBUS_DMACTL_HIGHWATER_SHIFT)
- | (fifobeg << HPC_PBUS_DMACTL_FIFOBEG_SHIFT)
- | (fifoend << HPC_PBUS_DMACTL_FIFOEND_SHIFT);
+ ctrl = HPC3_PBUS_DMACTL_RT
+ | HPC3_PBUS_DMACTL_ACT_LD
+ | (highwater << HPC3_PBUS_DMACTL_HIGHWATER_SHIFT)
+ | (fifobeg << HPC3_PBUS_DMACTL_FIFOBEG_SHIFT)
+ | (fifoend << HPC3_PBUS_DMACTL_FIFOEND_SHIFT);
/* Using PBUS CH0 for DAC DMA */
haltwo_write_indirect(sc, HAL2_IREG_DMA_DRV, 1, 0);
/* HAL2 is ready for action, now setup PBUS for DMA transfer */
- bus_space_write_4(sc->sc_st, sc->sc_dma_sh, HPC_PBUS_CH0_DP,
+ bus_space_write_4(sc->sc_st, sc->sc_dma_sh, HPC3_PBUS_CH0_DP,
sc->sc_dac.dma_seg.ds_addr);
- bus_space_write_4(sc->sc_st, sc->sc_dma_sh, HPC_PBUS_CH0_CTL,
- ctrl | HPC_PBUS_DMACTL_ACT);
+ bus_space_write_4(sc->sc_st, sc->sc_dma_sh, HPC3_PBUS_CH0_CTL,
+ ctrl | HPC3_PBUS_DMACTL_ACT);
/* Both HAL2 and PBUS have been setup, now start it up */
haltwo_read_indirect(sc, HAL2_IREG_DMA_PORT_EN, &tmp, NULL);
diff -r 16cd5cc0c6d3 -r c50489e1b756 sys/arch/sgimips/hpc/hpc.c
--- a/sys/arch/sgimips/hpc/hpc.c Thu Dec 30 23:03:19 2004 +0000
+++ b/sys/arch/sgimips/hpc/hpc.c Thu Dec 30 23:18:09 2004 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: hpc.c,v 1.30 2004/12/30 02:35:41 rumble Exp $ */
+/* $NetBSD: hpc.c,v 1.31 2004/12/30 23:18:09 rumble Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang
@@ -35,7 +35,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.30 2004/12/30 02:35:41 rumble Exp $");
+__KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.31 2004/12/30 23:18:09 rumble Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -71,7 +71,7 @@
{ "zsc",
HPC_BASE_ADDRESS_0,
/* XXX Magic numbers */
- HPC_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0,
+ HPC3_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0,
29,
HPCDEV_IP22 | HPCDEV_IP24 },
@@ -91,13 +91,13 @@
{ "pckbc",
HPC_BASE_ADDRESS_0,
- HPC_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0,
+ HPC3_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0,
28,
HPCDEV_IP22 | HPCDEV_IP24 },
{ "sq",
HPC_BASE_ADDRESS_0,
- HPC_ENET_DEVREGS, HPC_ENET_REGS,
+ HPC3_ENET_DEVREGS, HPC3_ENET_REGS,
3,
HPCDEV_IP22 | HPCDEV_IP24 },
@@ -133,13 +133,13 @@
{ "wdsc",
HPC_BASE_ADDRESS_0,
- HPC_SCSI0_DEVREGS, HPC_SCSI0_REGS,
+ HPC3_SCSI0_DEVREGS, HPC3_SCSI0_REGS,
1, /* XXX 1 = IRQ_LOCAL0 + 1 */
HPCDEV_IP22 | HPCDEV_IP24 },
{ "wdsc",
HPC_BASE_ADDRESS_0,
- HPC_SCSI1_DEVREGS, HPC_SCSI1_REGS,
+ HPC3_SCSI1_DEVREGS, HPC3_SCSI1_REGS,
2, /* XXX 2 = IRQ_LOCAL0 + 2 */
HPCDEV_IP22 },
@@ -157,13 +157,13 @@
{ "dsclock",
HPC_BASE_ADDRESS_0,
- HPC_PBUS_BBRAM, 0,
+ HPC3_PBUS_BBRAM, 0,
-1,
HPCDEV_IP22 | HPCDEV_IP24 },
{ "haltwo",
HPC_BASE_ADDRESS_0,
- HPC_PBUS_CH0_DEVREGS, HPC_PBUS_DMAREGS,
+ HPC3_PBUS_CH0_DEVREGS, HPC3_PBUS_DMAREGS,
8 + 4, /* XXX IRQ_LOCAL1 + 4 */
HPCDEV_IP22 | HPCDEV_IP24 },
@@ -253,68 +253,68 @@
static struct hpc_values hpc3_values = {
.revision 3,
- .scsi0_regs = HPC_SCSI0_REGS,
- .scsi0_regs_size = HPC_SCSI0_REGS_SIZE,
- .scsi0_cbp = HPC_SCSI0_CBP,
- .scsi0_ndbp = HPC_SCSI0_NDBP,
- .scsi0_bc = HPC_SCSI0_BC,
- .scsi0_ctl = HPC_SCSI0_CTL,
- .scsi0_gio = HPC_SCSI0_GIO,
- .scsi0_dev = HPC_SCSI0_DEV,
- .scsi0_dmacfg = HPC_SCSI0_DMACFG,
- .scsi0_piocfg = HPC_SCSI0_PIOCFG,
- .scsi1_regs = HPC_SCSI1_REGS,
- .scsi1_regs_size = HPC_SCSI1_REGS_SIZE,
- .scsi1_cbp = HPC_SCSI1_CBP,
- .scsi1_ndbp = HPC_SCSI1_NDBP,
- .scsi1_bc = HPC_SCSI1_BC,
- .scsi1_ctl = HPC_SCSI1_CTL,
- .scsi1_gio = HPC_SCSI1_GIO,
- .scsi1_dev = HPC_SCSI1_DEV,
- .scsi1_dmacfg = HPC_SCSI1_DMACFG,
- .scsi1_piocfg = HPC_SCSI1_PIOCFG,
- .dmactl_dir = HPC_DMACTL_DIR,
- .dmactl_flush = HPC_DMACTL_FLUSH,
- .dmactl_active = HPC_DMACTL_ACTIVE,
- .dmactl_reset = HPC_DMACTL_RESET,
- .enet_regs = HPC_ENET_REGS,
- .enet_regs_size = HPC_ENET_REGS_SIZE,
+ .scsi0_regs = HPC3_SCSI0_REGS,
+ .scsi0_regs_size = HPC3_SCSI0_REGS_SIZE,
+ .scsi0_cbp = HPC3_SCSI0_CBP,
+ .scsi0_ndbp = HPC3_SCSI0_NDBP,
+ .scsi0_bc = HPC3_SCSI0_BC,
+ .scsi0_ctl = HPC3_SCSI0_CTL,
+ .scsi0_gio = HPC3_SCSI0_GIO,
+ .scsi0_dev = HPC3_SCSI0_DEV,
+ .scsi0_dmacfg = HPC3_SCSI0_DMACFG,
+ .scsi0_piocfg = HPC3_SCSI0_PIOCFG,
+ .scsi1_regs = HPC3_SCSI1_REGS,
+ .scsi1_regs_size = HPC3_SCSI1_REGS_SIZE,
+ .scsi1_cbp = HPC3_SCSI1_CBP,
+ .scsi1_ndbp = HPC3_SCSI1_NDBP,
+ .scsi1_bc = HPC3_SCSI1_BC,
+ .scsi1_ctl = HPC3_SCSI1_CTL,
+ .scsi1_gio = HPC3_SCSI1_GIO,
+ .scsi1_dev = HPC3_SCSI1_DEV,
+ .scsi1_dmacfg = HPC3_SCSI1_DMACFG,
+ .scsi1_piocfg = HPC3_SCSI1_PIOCFG,
+ .dmactl_dir = HPC3_DMACTL_DIR,
+ .dmactl_flush = HPC3_DMACTL_FLUSH,
+ .dmactl_active = HPC3_DMACTL_ACTIVE,
+ .dmactl_reset = HPC3_DMACTL_RESET,
+ .enet_regs = HPC3_ENET_REGS,
+ .enet_regs_size = HPC3_ENET_REGS_SIZE,
.enet_intdelay = 0,
.enet_intdelayval = 0,
- .enetr_cbp = HPC_ENETR_CBP,
- .enetr_ndbp = HPC_ENETR_NDBP,
- .enetr_bc = HPC_ENETR_BC,
- .enetr_ctl = HPC_ENETR_CTL,
- .enetr_ctl_active = ENETR_CTL_ACTIVE,
- .enetr_reset = HPC_ENETR_RESET,
- .enetr_dmacfg = HPC_ENETR_DMACFG,
- .enetr_piocfg = HPC_ENETR_PIOCFG,
- .enetx_cbp = HPC_ENETX_CBP,
- .enetx_ndbp = HPC_ENETX_NDBP,
- .enetx_bc = HPC_ENETX_BC,
- .enetx_ctl = HPC_ENETX_CTL,
- .enetx_ctl_active = ENETX_CTL_ACTIVE,
- .enetx_dev = HPC_ENETX_DEV,
- .enetr_fifo = HPC_ENETR_FIFO,
- .enetr_fifo_size = HPC_ENETR_FIFO_SIZE,
- .enetx_fifo = HPC_ENETX_FIFO,
- .enetx_fifo_size = HPC_ENETX_FIFO_SIZE,
- .scsi0_devregs_size = HPC_SCSI0_DEVREGS_SIZE,
- .scsi1_devregs_size = HPC_SCSI1_DEVREGS_SIZE,
- .enet_devregs = HPC_ENET_DEVREGS,
- .enet_devregs_size = HPC_ENET_DEVREGS_SIZE,
- .pbus_fifo = HPC_PBUS_FIFO,
- .pbus_fifo_size = HPC_PBUS_FIFO_SIZE,
- .pbus_bbram = HPC_PBUS_BBRAM,
+ .enetr_cbp = HPC3_ENETR_CBP,
+ .enetr_ndbp = HPC3_ENETR_NDBP,
+ .enetr_bc = HPC3_ENETR_BC,
+ .enetr_ctl = HPC3_ENETR_CTL,
+ .enetr_ctl_active = HPC3_ENETR_CTL_ACTIVE,
+ .enetr_reset = HPC3_ENETR_RESET,
+ .enetr_dmacfg = HPC3_ENETR_DMACFG,
+ .enetr_piocfg = HPC3_ENETR_PIOCFG,
+ .enetx_cbp = HPC3_ENETX_CBP,
+ .enetx_ndbp = HPC3_ENETX_NDBP,
+ .enetx_bc = HPC3_ENETX_BC,
+ .enetx_ctl = HPC3_ENETX_CTL,
+ .enetx_ctl_active = HPC3_ENETX_CTL_ACTIVE,
+ .enetx_dev = HPC3_ENETX_DEV,
+ .enetr_fifo = HPC3_ENETR_FIFO,
+ .enetr_fifo_size = HPC3_ENETR_FIFO_SIZE,
+ .enetx_fifo = HPC3_ENETX_FIFO,
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