[src/trunk]: src/sys/arch/x86/include Add the following bit definitions from ...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/c9b6ea113082
branches:  trunk
changeset: 461164:c9b6ea113082
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Sun Nov 17 15:31:05 2019 +0000

description:
Add the following bit definitions from the latest Intel SDM:
 - CET shadow stack
 - Fast Short REP MOV
 - Hybrid part
 - CET Indirect Branch Tracking

diffstat:

 sys/arch/x86/include/specialreg.h |  12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)

diffs (50 lines):

diff -r 70221f918c98 -r c9b6ea113082 sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Sun Nov 17 14:07:00 2019 +0000
+++ b/sys/arch/x86/include/specialreg.h Sun Nov 17 15:31:05 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.157 2019/11/12 18:00:13 maxv Exp $    */
+/*     $NetBSD: specialreg.h,v 1.158 2019/11/17 15:31:05 msaitoh Exp $ */
 
 /*
  * Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -447,6 +447,7 @@
 #define CPUID_SEF_OSPKE                __BIT(4)  /* OS has set CR4.PKE to ena. protec. keys */
 #define CPUID_SEF_WAITPKG      __BIT(5)  /* TPAUSE,UMONITOR,UMWAIT */
 #define CPUID_SEF_AVX512_VBMI2 __BIT(6)  /* AVX-512 Vector Byte Manipulation 2 */
+#define CPUID_SEF_CET_SS       __BIT(7)  /* CET shadow stack */
 #define CPUID_SEF_GFNI         __BIT(8)
 #define CPUID_SEF_VAES         __BIT(9)
 #define CPUID_SEF_VPCLMULQDQ   __BIT(10)
@@ -462,7 +463,7 @@
 
 #define CPUID_SEF_FLAGS1       "\177\20" \
        "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0"    \
-       "b\4OSPKE\0"    "b\5WAITPKG\0"  "b\6AVX512_VBMI2\0"                   \
+       "b\4OSPKE\0"    "b\5WAITPKG\0"  "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \
        "b\10GFNI\0"    "b\11VAES\0"    "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\
        "b\14AVX512_BITALG\0"           "b\16AVX512_VPOPCNTDQ\0"        \
        "f\21\5MAWAU\0"                                                 \
@@ -473,8 +474,11 @@
 /* %edx */
 #define CPUID_SEF_AVX512_4VNNIW        __BIT(2)
 #define CPUID_SEF_AVX512_4FMAPS        __BIT(3)
+#define CPUID_SEF_FSREP_MOV    __BIT(4)  /* Fast Short REP MOV */
 #define CPUID_SEF_MD_CLEAR     __BIT(10)
 #define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */
+#define CPUID_SEF_HYBRID       __BIT(15) /* Hybrid part */
+#define CPUID_SEF_CET_IBT      __BIT(20) /* CET Indirect Branch Tracking */
 #define CPUID_SEF_IBRS         __BIT(26) /* IBRS / IBPB Speculation Control */
 #define CPUID_SEF_STIBP                __BIT(27) /* STIBP Speculation Control */
 #define CPUID_SEF_L1D_FLUSH    __BIT(28) /* IA32_FLUSH_CMD MSR */
@@ -484,8 +488,10 @@
 
 #define CPUID_SEF_FLAGS2       "\20" \
                                "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
+       "\5" "FSREP_MOV"                                                \
                                "\13" "MD_CLEAR"                        \
-                       "\16" "TSX_FORCE_ABORT"                         \
+                       "\16" "TSX_FORCE_ABORT"         "\20" "HYBRID"  \
+       "\25" "CET_IBT"                                                 \
        "\33" "IBRS"    "\34" "STIBP"                                   \
        "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP"        "\40" "SSBD"