[src/trunk]: src/sys/dev/mii - Define IPGPHY_SCR's address.

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/a5354e4f9c5d
branches:  trunk
changeset: 460987:a5354e4f9c5d
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Tue Nov 12 14:07:09 2019 +0000

description:
- Define IPGPHY_SCR's address.
- Whitespace fix.

diffstat:

 sys/dev/mii/ipgphyreg.h |  34 +++++++++++++++++-----------------
 1 files changed, 17 insertions(+), 17 deletions(-)

diffs (69 lines):

diff -r 7f727c004256 -r a5354e4f9c5d sys/dev/mii/ipgphyreg.h
--- a/sys/dev/mii/ipgphyreg.h   Tue Nov 12 13:17:43 2019 +0000
+++ b/sys/dev/mii/ipgphyreg.h   Tue Nov 12 14:07:09 2019 +0000
@@ -36,48 +36,48 @@
  */
 
 /* PHY specific control & status register. IP1001 only. */
-#define IPGPHY_SCSR                    0x10
-#define IPGPHY_SCSR_RXPHASE_SEL        0x0001
-#define IPGPHY_SCSR_TXPHASE_SEL        0x0002
+#define IPGPHY_SCSR            0x10
+#define IPGPHY_SCSR_RXPHASE_SEL                0x0001
+#define IPGPHY_SCSR_TXPHASE_SEL                0x0002
 #define IPGPHY_SCSR_REPEATOR_MODE      0x0004
 #define IPGPHY_SCSR_RESERVED1_DEF      0x0008
 #define IPGPHY_SCSR_RXCLK_DRV_MASK     0x0060
 #define IPGPHY_SCSR_RXCLK_DRV_DEF      0x0040
 #define IPGPHY_SCSR_RXD_DRV_MASK       0x0180
-#define IPGPHY_SCSR_RXD_DRV_DEF        0x0100
-#define IPGPHY_SCSR_JABBER_ENB 0x0200
+#define IPGPHY_SCSR_RXD_DRV_DEF                0x0100
+#define IPGPHY_SCSR_JABBER_ENB         0x0200
 #define IPGPHY_SCSR_HEART_BEAT_ENB     0x0400
 #define IPGPHY_SCSR_DOWNSHIFT_ENB      0x0800
 #define IPGPHY_SCSR_RESERVED2_DEF      0x1000
-#define IPGPHY_SCSR_LED_DRV_4MA        0x0000
-#define IPGPHY_SCSR_LED_DRV_8MA        0x2000
+#define IPGPHY_SCSR_LED_DRV_4MA                0x0000
+#define IPGPHY_SCSR_LED_DRV_8MA                0x2000
 #define IPGPHY_SCSR_LED_MODE_MASK      0xC000
 #define IPGPHY_SCSR_LED_MODE_DEF       0x0000
 
 /* PHY link status register. IP1001 only. */
-#define IPGPHY_LSR                     0x11
-#define IPGPHY_LSR_JABBER_DET  0x0200
+#define IPGPHY_LSR             0x11
+#define IPGPHY_LSR_JABBER_DET          0x0200
 #define IPGPHY_LSR_APS_SLEEP           0x0400
-#define IPGPHY_LSR_MDIX                0x0800
-#define IPGPHY_LSR_FULL_DUPLEX 0x1000
+#define IPGPHY_LSR_MDIX                        0x0800
+#define IPGPHY_LSR_FULL_DUPLEX         0x1000
 #define IPGPHY_LSR_SPEED_10            0x0000
 #define IPGPHY_LSR_SPEED_100           0x2000
-#define IPGPHY_LSR_SPEED_1000  0x4000
-#define IPGPHY_LSR_SPEED_MASK  0x6000
+#define IPGPHY_LSR_SPEED_1000          0x4000
+#define IPGPHY_LSR_SPEED_MASK          0x6000
 #define IPGPHY_LSR_LINKUP              0x8000
 
 /* PHY specific control register 2. IP1001 only. */
-#define IPGPHY_SCR
+#define IPGPHY_SCR             0x14
 #define IPGPHY_SCR_SEW_RATE_MASK       0x0003
-#define IPGPHY_SCR_SEW_RATE_DEF        0x0003
-#define IPGPHY_SCR_AUTO_XOVER  0x0004
+#define IPGPHY_SCR_SEW_RATE_DEF                0x0003
+#define IPGPHY_SCR_AUTO_XOVER          0x0004
 #define IPGPHY_SCR_SPEED_10_100_ENB    0x0040
 #define IPGPHY_SCR_FIFO_LATENCY_2      0x0000
 #define IPGPHY_SCR_FIFO_LATENCY_3      0x0080
 #define IPGPHY_SCR_FIFO_LATENCY_4      0x0100
 #define IPGPHY_SCR_FIFO_LATENCY_5      0x0180
 #define IPGPHY_SCR_MDIX_ENB            0x0200
-#define IPGPHY_SCR_RESERVED_DEF        0x0400
+#define IPGPHY_SCR_RESERVED_DEF                0x0400
 #define IPGPHY_SCR_APS_ON              0x0800
 
 #endif /* _DEV_MII_IPGPHYREG_H_ */