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[src/trunk]: src/sys/arch/arm KNF. No functional change.
details: https://anonhg.NetBSD.org/src/rev/f69a8207f0fd
branches: trunk
changeset: 451619:f69a8207f0fd
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Wed May 29 05:05:24 2019 +0000
description:
KNF. No functional change.
diffstat:
sys/arch/arm/omap/if_cpsw.c | 28 ++++++++++++++++++----------
sys/arch/arm/omap/omapl1x_emac.c | 11 ++++++-----
sys/arch/arm/ti/if_cpsw.c | 28 ++++++++++++++++++----------
3 files changed, 42 insertions(+), 25 deletions(-)
diffs (215 lines):
diff -r fb4f18075715 -r f69a8207f0fd sys/arch/arm/omap/if_cpsw.c
--- a/sys/arch/arm/omap/if_cpsw.c Wed May 29 03:25:46 2019 +0000
+++ b/sys/arch/arm/omap/if_cpsw.c Wed May 29 05:05:24 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_cpsw.c,v 1.23 2019/03/05 08:25:01 msaitoh Exp $ */
+/* $NetBSD: if_cpsw.c,v 1.24 2019/05/29 05:05:24 msaitoh Exp $ */
/*
* Copyright (c) 2013 Jonathan A. Kollasch
@@ -53,7 +53,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.23 2019/03/05 08:25:01 msaitoh Exp $");
+__KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.24 2019/05/29 05:05:24 msaitoh Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -877,11 +877,13 @@
/* Reset wrapper */
cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1);
- while(cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1);
+ while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1)
+ ;
/* Reset SS */
cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1);
- while(cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1);
+ while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1)
+ ;
/* Clear table and enable ALE */
cpsw_write_4(sc, CPSW_ALE_CONTROL,
@@ -893,7 +895,8 @@
/* Reset */
cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1);
- while(cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1);
+ while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1)
+ ;
/* Set Slave Mapping */
cpsw_write_4(sc, CPSW_SL_RX_PRI_MAP(i), 0x76543210);
cpsw_write_4(sc, CPSW_PORT_P_TX_PRI_MAP(i+1), 0x33221100);
@@ -930,7 +933,8 @@
cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7);
cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
- while(cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1);
+ while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1)
+ ;
for (i = 0; i < 8; i++) {
cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0);
@@ -1046,20 +1050,24 @@
/* Reset wrapper */
cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1);
- while(cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1);
+ while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1)
+ ;
/* Reset SS */
cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1);
- while(cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1);
+ while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1)
+ ;
for (i = 0; i < CPSW_ETH_PORTS; i++) {
cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1);
- while(cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1);
+ while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1)
+ ;
}
/* Reset CPDMA */
cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
- while(cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1);
+ while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1)
+ ;
/* Release any queued transmit buffers. */
for (i = 0; i < CPSW_NTXDESCS; i++) {
diff -r fb4f18075715 -r f69a8207f0fd sys/arch/arm/omap/omapl1x_emac.c
--- a/sys/arch/arm/omap/omapl1x_emac.c Wed May 29 03:25:46 2019 +0000
+++ b/sys/arch/arm/omap/omapl1x_emac.c Wed May 29 05:05:24 2019 +0000
@@ -30,7 +30,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omapl1x_emac.c,v 1.8 2019/01/22 03:42:25 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omapl1x_emac.c,v 1.9 2019/05/29 05:05:24 msaitoh Exp $");
#include "opt_omapl1x.h"
@@ -263,7 +263,7 @@
{
u_int tries;
- for(tries = 0; tries < 1000; tries++) {
+ for (tries = 0; tries < 1000; tries++) {
if ((EMAC_READ(sc, MACMDIOUSERACCESS0) & USERACCESS_GO) == 0)
return 0;
@@ -1042,7 +1042,8 @@
EMAC_WRITE(sc, MACHASH2, 0);
EMAC_WRITE(sc, MACSOFTRESET, 1);
- while (EMAC_READ(sc, MACSOFTRESET) == 1);
+ while (EMAC_READ(sc, MACSOFTRESET) == 1)
+ ;
/* Till we figure out mcast, do this */
EMAC_WRITE(sc, MACHASH1, 0xffffffff);
@@ -1180,7 +1181,7 @@
{
int i;
struct emac_cppi_bd *ptr = desc_base_ptr;
-
+
for (i = 0; i < ndescs; i++)
desc[i] = ptr + i;
}
@@ -1279,7 +1280,7 @@
SIMPLEQ_INIT(&tx_chan->free_head);
SIMPLEQ_INIT(&tx_chan->inuse_head);
for (i = 0; i < EMAC_NTXDESCS; i++) {
- /*
+ /*
* Ok, we keep this simple, one dma segment per tx dma map.
* This makes the mapping of the desc's and the dma map's
* pretty straightforward.
diff -r fb4f18075715 -r f69a8207f0fd sys/arch/arm/ti/if_cpsw.c
--- a/sys/arch/arm/ti/if_cpsw.c Wed May 29 03:25:46 2019 +0000
+++ b/sys/arch/arm/ti/if_cpsw.c Wed May 29 05:05:24 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_cpsw.c,v 1.4 2019/03/05 08:25:02 msaitoh Exp $ */
+/* $NetBSD: if_cpsw.c,v 1.5 2019/05/29 05:05:24 msaitoh Exp $ */
/*
* Copyright (c) 2013 Jonathan A. Kollasch
@@ -53,7 +53,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.4 2019/03/05 08:25:02 msaitoh Exp $");
+__KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.5 2019/05/29 05:05:24 msaitoh Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -915,11 +915,13 @@
/* Reset wrapper */
cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1);
- while(cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1);
+ while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1)
+ ;
/* Reset SS */
cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1);
- while(cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1);
+ while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1)
+ ;
/* Clear table and enable ALE */
cpsw_write_4(sc, CPSW_ALE_CONTROL,
@@ -931,7 +933,8 @@
/* Reset */
cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1);
- while(cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1);
+ while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1)
+ ;
/* Set Slave Mapping */
cpsw_write_4(sc, CPSW_SL_RX_PRI_MAP(i), 0x76543210);
cpsw_write_4(sc, CPSW_PORT_P_TX_PRI_MAP(i+1), 0x33221100);
@@ -968,7 +971,8 @@
cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7);
cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
- while(cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1);
+ while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1)
+ ;
for (i = 0; i < 8; i++) {
cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0);
@@ -1084,20 +1088,24 @@
/* Reset wrapper */
cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1);
- while(cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1);
+ while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1)
+ ;
/* Reset SS */
cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1);
- while(cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1);
+ while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1)
+ ;
for (i = 0; i < CPSW_ETH_PORTS; i++) {
cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1);
- while(cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1);
+ while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1)
+ ;
}
/* Reset CPDMA */
cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
- while(cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1);
+ while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1)
+ ;
/* Release any queued transmit buffers. */
for (i = 0; i < CPSW_NTXDESCS; i++) {
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