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[src/netbsd-8]: src Pull up following revision(s) (requested by msaitoh in ti...



details:   https://anonhg.NetBSD.org/src/rev/f377a36e945d
branches:  netbsd-8
changeset: 434921:f377a36e945d
user:      martin <martin%NetBSD.org@localhost>
date:      Mon Apr 16 14:25:49 2018 +0000

description:
Pull up following revision(s) (requested by msaitoh in ticket #764):

        sys/dev/pci/if_wm.c: revision 1.567
        sys/dev/pci/if_wm.c: revision 1.568
        sys/dev/pci/if_wm.c: revision 1.569
        sys/dev/pci/if_wmvar.h: revision 1.38
        sys/dev/pci/if_wm.c: revision 1.570
        sys/dev/pci/if_wm.c: revision 1.571
        sys/dev/pci/if_wm.c: revision 1.572
        share/man/man4/wm.4: revision 1.40
        sys/dev/pci/if_wmreg.h: revision 1.106
        sys/dev/pci/if_wmreg.h: revision 1.107

SW PHY Config Enable bit for ICH8 B0 stepping is not bit 1 but bit 0.

 No binary change:
- Sort registers.
- Lowercase hexadecimal value.

 On PCH_SPT (and newer), FLASH access should be done by 32bit.
Especially for ICH_FLASH_HSFCTL register, it's located at 0x0006, so
it should be accessed via ICH_FLASH_HSFSTS(0x0004) and use shift or mask.

 Our PCH_SPT part of wm_nvm_valid_bank_detect_ich8lan() was based on
FreeBSD r287467. After that, they reverted it and committed the different
code in r287762. r287762's bank detect code didn't work for us because our wm
dirver had a problem in flash access. The problem was fixed in if_wm.c rev.
1.567, so we can use the new way now.

 If the extended configration size in the EXTCNFSIZE register is 0, don't
continue.
 Add PCH_CNP support (I219 with Intel 300 series chipset).
It's required more test, so it's disabled by default.

 Enable I219.

 I354 uses an external PHY, so don't use wm_set_eee_i350().

diffstat:

 share/man/man4/wm.4    |    6 +-
 sys/dev/pci/if_wm.c    |  204 ++++++++++++++++++++++++++++++++++++------------
 sys/dev/pci/if_wmreg.h |   70 ++++++++--------
 sys/dev/pci/if_wmvar.h |    5 +-
 4 files changed, 195 insertions(+), 90 deletions(-)

diffs (truncated from 882 to 300 lines):

diff -r d955eda41e00 -r f377a36e945d share/man/man4/wm.4
--- a/share/man/man4/wm.4       Mon Apr 16 14:21:48 2018 +0000
+++ b/share/man/man4/wm.4       Mon Apr 16 14:25:49 2018 +0000
@@ -1,4 +1,4 @@
-.\"    $NetBSD: wm.4,v 1.36.4.1 2018/02/05 15:07:30 martin Exp $
+.\"    $NetBSD: wm.4,v 1.36.4.2 2018/04/16 14:25:49 martin Exp $
 .\"
 .\" Copyright 2002, 2003 Wasabi Systems, Inc.
 .\" All rights reserved.
@@ -33,7 +33,7 @@
 .\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 .\" POSSIBILITY OF SUCH DAMAGE.
 .\"
-.Dd January 18, 2018
+.Dd April 13, 2018
 .Dt WM 4
 .Os
 .Sh NAME
@@ -152,6 +152,8 @@
 Intel I211 Ethernet
 .It
 Intel I217 and I218 Ethernet
+.It
+Intel I219 Ethernet (with Intel [123]00 series chipset)
 .El
 .Pp
 In addition to Intel's own
diff -r d955eda41e00 -r f377a36e945d sys/dev/pci/if_wm.c
--- a/sys/dev/pci/if_wm.c       Mon Apr 16 14:21:48 2018 +0000
+++ b/sys/dev/pci/if_wm.c       Mon Apr 16 14:25:49 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_wm.c,v 1.508.4.16 2018/03/06 10:59:04 martin Exp $  */
+/*     $NetBSD: if_wm.c,v 1.508.4.17 2018/04/16 14:25:49 martin Exp $  */
 
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -83,7 +83,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.508.4.16 2018/03/06 10:59:04 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.508.4.17 2018/04/16 14:25:49 martin Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_net_mpsafe.h"
@@ -1485,7 +1485,6 @@
        { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_I218_LM3,
          "I218 LM Ethernet Connection",
          WM_T_PCH_LPT,         WMP_F_COPPER },
-#if 0
        { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_I219_V,
          "I219 V Ethernet Connection",
          WM_T_PCH_SPT,         WMP_F_COPPER },
@@ -1513,7 +1512,18 @@
        { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_I219_LM5,
          "I219 LM Ethernet Connection",
          WM_T_PCH_SPT,         WMP_F_COPPER },
-#endif
+       { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_I219_V6,
+         "I219 V Ethernet Connection",
+         WM_T_PCH_CNP,         WMP_F_COPPER },
+       { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_I219_V7,
+         "I219 V Ethernet Connection",
+         WM_T_PCH_CNP,         WMP_F_COPPER },
+       { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_I219_LM6,
+         "I219 LM Ethernet Connection",
+         WM_T_PCH_CNP,         WMP_F_COPPER },
+       { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_I219_LM7,
+         "I219 LM Ethernet Connection",
+         WM_T_PCH_CNP,         WMP_F_COPPER },
        { 0,                    0,
          NULL,
          0,                    0 },
@@ -1986,7 +1996,8 @@
                    && (sc->sc_type != WM_T_PCH)
                    && (sc->sc_type != WM_T_PCH2)
                    && (sc->sc_type != WM_T_PCH_LPT)
-                   && (sc->sc_type != WM_T_PCH_SPT)) {
+                   && (sc->sc_type != WM_T_PCH_SPT)
+                   && (sc->sc_type != WM_T_PCH_CNP)) {
                        /* ICH* and PCH* have no PCIe capability registers */
                        if (pci_get_capability(pa->pa_pc, pa->pa_tag,
                                PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff,
@@ -2233,6 +2244,7 @@
                sc->nvm.release = wm_put_nvm_ich8lan;
                break;
        case WM_T_PCH_SPT:
+       case WM_T_PCH_CNP:
                sc->nvm.read = wm_nvm_read_spt;
                /* SPT has no GFPREG; flash registers mapped through BAR0 */
                sc->sc_flags |= WM_F_EEPROM_FLASH;
@@ -2468,6 +2480,7 @@
        case WM_T_PCH2:
        case WM_T_PCH_LPT:
        case WM_T_PCH_SPT:
+       case WM_T_PCH_CNP:
                /* XXX The funcid should be checked on some devices */
                apme_mask = WUC_APME;
                eeprom_data = CSR_READ(sc, WMREG_WUC);
@@ -2577,7 +2590,8 @@
        if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9
            || sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH
            || sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_PCH_LPT
-           || sc->sc_type == WM_T_PCH_SPT || sc->sc_type == WM_T_82573
+           || sc->sc_type == WM_T_PCH_SPT || sc->sc_type == WM_T_PCH_CNP
+           || sc->sc_type == WM_T_82573
            || sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) {
                /* Copper only */
        } else if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
@@ -2731,6 +2745,7 @@
        case WM_T_PCH2: /* PCH2 supports 9K frame size */
        case WM_T_PCH_LPT:
        case WM_T_PCH_SPT:
+       case WM_T_PCH_CNP:
                /* XXX limited to 9234 */
                sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
                break;
@@ -3374,6 +3389,7 @@
        case WM_T_PCH2:
        case WM_T_PCH_LPT:
        case WM_T_PCH_SPT:
+       case WM_T_PCH_CNP:
                if (idx == 0) {
                        CSR_WRITE(sc, WMREG_CORDOVA_RAL(idx), ral_lo);
                        CSR_WRITE_FLUSH(sc);
@@ -3431,7 +3447,7 @@
        if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
            || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
            || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
-           || (sc->sc_type == WM_T_PCH_SPT)) {
+           || (sc->sc_type == WM_T_PCH_SPT) || (sc->sc_type == WM_T_PCH_CNP)){
                hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) |
                    (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]);
                return (hash & 0x3ff);
@@ -3486,7 +3502,8 @@
                size = WM_RAL_TABSIZE_ICH8;
        else if (sc->sc_type == WM_T_PCH2)
                size = WM_RAL_TABSIZE_PCH2;
-       else if ((sc->sc_type == WM_T_PCH_LPT) ||(sc->sc_type == WM_T_PCH_SPT))
+       else if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)
+           || (sc->sc_type == WM_T_PCH_CNP))
                size = WM_RAL_TABSIZE_PCH_LPT;
        else if (sc->sc_type == WM_T_82575)
                size = WM_RAL_TABSIZE_82575;
@@ -3498,7 +3515,8 @@
                size = WM_RAL_TABSIZE;
        wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0);
 
-       if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)) {
+       if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)
+           || (sc->sc_type == WM_T_PCH_CNP)) {
                i = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM), FWSM_WLOCK_MAC);
                switch (i) {
                case 0:
@@ -3523,7 +3541,7 @@
        if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
            || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
            || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
-           || (sc->sc_type == WM_T_PCH_SPT))
+           || (sc->sc_type == WM_T_PCH_SPT) || (sc->sc_type == WM_T_PCH_CNP))
                size = WM_ICH8_MC_TABSIZE;
        else
                size = WM_MC_TABSIZE;
@@ -3556,7 +3574,8 @@
                    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
                    || (sc->sc_type == WM_T_PCH2)
                    || (sc->sc_type == WM_T_PCH_LPT)
-                   || (sc->sc_type == WM_T_PCH_SPT))
+                   || (sc->sc_type == WM_T_PCH_SPT)
+                   || (sc->sc_type == WM_T_PCH_CNP))
                        reg &= 0x1f;
                else
                        reg &= 0x7f;
@@ -3698,6 +3717,7 @@
        case WM_T_PCH2:
        case WM_T_PCH_LPT:
        case WM_T_PCH_SPT:
+       case WM_T_PCH_CNP:
                for (i = 0; i < WM_ICH8_LAN_INIT_TIMEOUT; i++) {
                        reg = CSR_READ(sc, WMREG_STATUS);
                        if ((reg & STATUS_LAN_INIT_DONE) != 0)
@@ -3784,6 +3804,7 @@
        case WM_T_PCH2:
        case WM_T_PCH_LPT:
        case WM_T_PCH_SPT:
+       case WM_T_PCH_CNP:
                delay(10*1000);
                if (sc->sc_type >= WM_T_ICH10)
                        wm_lan_init_done(sc);
@@ -3903,6 +3924,7 @@
        case WM_T_PCH2:
        case WM_T_PCH_LPT:
        case WM_T_PCH_SPT:
+       case WM_T_PCH_CNP:
                sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M;
                break;
        default:
@@ -3931,6 +3953,8 @@
        
        reg = CSR_READ(sc, WMREG_EXTCNFSIZE);
        cnf_size = __SHIFTOUT(reg, EXTCNFSIZE_LENGTH);
+       if (cnf_size == 0)
+               goto release;
 
        if (((sc->sc_type == WM_T_PCH)
                && ((extcnfctr & EXTCNFCTR_OEM_WRITE_ENABLE) == 0))
@@ -4113,6 +4137,7 @@
                case WM_T_PCH2:
                case WM_T_PCH_LPT:
                case WM_T_PCH_SPT:
+               case WM_T_PCH_CNP:
                        /* TARC0 */
                        if (sc->sc_type == WM_T_ICH8) {
                                /* Set TARC0 bits 29 and 28 */
@@ -4420,9 +4445,10 @@
                    PBA_14K : PBA_10K;
                break;
        case WM_T_PCH:
-       case WM_T_PCH2:
+       case WM_T_PCH2: /* XXX 14K? */
        case WM_T_PCH_LPT:
        case WM_T_PCH_SPT:
+       case WM_T_PCH_CNP:
                sc->sc_pba = PBA_26K;
                break;
        default:
@@ -4547,6 +4573,7 @@
        case WM_T_PCH2:
        case WM_T_PCH_LPT:
        case WM_T_PCH_SPT:
+       case WM_T_PCH_CNP:
                reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
                if (wm_phy_resetisblocked(sc) == false) {
                        /*
@@ -4678,6 +4705,7 @@
        case WM_T_PCH2:
        case WM_T_PCH_LPT:
        case WM_T_PCH_SPT:
+       case WM_T_PCH_CNP:
                break;
        default:
                panic("%s: unknown type\n", __func__);
@@ -4726,7 +4754,7 @@
        if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
            || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
            || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
-           || (sc->sc_type == WM_T_PCH_SPT)) {
+           || (sc->sc_type == WM_T_PCH_SPT) || (sc->sc_type == WM_T_PCH_CNP)){
                reg = CSR_READ(sc, WMREG_KABGTXD);
                reg |= KABGTXD_BGSQLBIAS;
                CSR_WRITE(sc, WMREG_KABGTXD, reg);
@@ -4735,7 +4763,12 @@
        /* reload sc_ctrl */
        sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
 
-       if ((sc->sc_type >= WM_T_I350) && (sc->sc_type <= WM_T_I211))
+       if (sc->sc_type == WM_T_I354) {
+#if 0
+               /* I354 uses an external PHY */
+               wm_set_eee_i354(sc);
+#endif
+       } else if ((sc->sc_type >= WM_T_I350) && (sc->sc_type <= WM_T_I211))
                wm_set_eee_i350(sc);
 
        /*
@@ -5409,7 +5442,7 @@
        if ((sc->sc_flags & WM_F_HAS_AMT) != 0)
                wm_get_hw_control(sc);
 
-       if ((sc->sc_type == WM_T_PCH_SPT) &&
+       if ((sc->sc_type >= WM_T_PCH_SPT) &&
            pci_intr_type(sc->sc_pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_INTX)
                wm_legacy_irq_quirk_spt(sc);
 
@@ -5480,7 +5513,7 @@
        if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
            && (sc->sc_type != WM_T_ICH10) && (sc->sc_type != WM_T_PCH)
            && (sc->sc_type != WM_T_PCH2) && (sc->sc_type != WM_T_PCH_LPT)
-           && (sc->sc_type != WM_T_PCH_SPT)) {
+           && (sc->sc_type != WM_T_PCH_SPT) && (sc->sc_type != WM_T_PCH_CNP)){
                CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST);
                CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
                CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
@@ -5515,6 +5548,7 @@
                case WM_T_PCH2:
                case WM_T_PCH_LPT:
                case WM_T_PCH_SPT:
+               case WM_T_PCH_CNP:
                        /*
                         * Set the mac to wait the maximum time between each
                         * iteration and increase the max iterations when
@@ -5851,6 +5885,7 @@
                break;
        case WM_T_PCH_LPT:
        case WM_T_PCH_SPT:
+       case WM_T_PCH_CNP:
                reg = CSR_READ(sc, WMREG_PBECCSTS);
                reg |= PBECCSTS_UNCORR_ECC_ENABLE;
                CSR_WRITE(sc, WMREG_PBECCSTS, reg);
@@ -8657,8 +8692,7 @@



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