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[src/trunk]: src/sys/dev/pci Decode IOMMU capability of PCI secure device cap...



details:   https://anonhg.NetBSD.org/src/rev/759e2223fd60
branches:  trunk
changeset: 356737:759e2223fd60
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Tue Oct 10 03:11:01 2017 +0000

description:
Decode IOMMU capability of PCI secure device capability. From "AMD I/O
Virtualization Technology(IOMMU) Specification (#48882) Revision 3.00".

diffstat:

 sys/dev/pci/pci_subr.c |  91 +++++++++++++++++++++++++++++++++++++++++++++++--
 sys/dev/pci/pcireg.h   |  39 ++++++++++++++++++++-
 2 files changed, 124 insertions(+), 6 deletions(-)

diffs (173 lines):

diff -r 814627078988 -r 759e2223fd60 sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c    Tue Oct 10 03:05:29 2017 +0000
+++ b/sys/dev/pci/pci_subr.c    Tue Oct 10 03:11:01 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pci_subr.c,v 1.191 2017/10/05 06:14:30 msaitoh Exp $   */
+/*     $NetBSD: pci_subr.c,v 1.192 2017/10/10 03:11:01 msaitoh Exp $   */
 
 /*
  * Copyright (c) 1997 Zubin D. Dittia.  All rights reserved.
@@ -40,7 +40,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.191 2017/10/05 06:14:30 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.192 2017/10/10 03:11:01 msaitoh Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_pci.h"
@@ -1530,7 +1530,90 @@
 }
 
 /* XXX pci_conf_print_agp8_cap */
-/* XXX pci_conf_print_secure_cap */
+static void
+pci_conf_print_secure_cap(const pcireg_t *regs, int capoff)
+{
+       pcireg_t reg, reg2, val;
+       bool havemisc1;
+
+       printf("\n  Secure Capability Register\n");
+       reg = regs[o2i(capoff + PCI_SECURE_CAP)];
+       val = __SHIFTOUT(reg, PCI_SECURE_CAP_TYPE);
+       printf("    Capability block type: ");
+       /* I know IOMMU Only */
+       if (val == PCI_SECURE_CAP_TYPE_IOMMU)
+               printf("IOMMU\n");
+       else {
+               printf("0x%x(unknown)\n", val);
+               return;
+       }
+
+       val = __SHIFTOUT(reg, PCI_SECURE_CAP_REV);
+       printf("    Capability revision: 0x%02x", val);
+       if (val == PCI_SECURE_CAP_REV_IOMMU)
+               printf("IOMMU\n");
+       else {
+               printf("(unknown)\n");
+               return;
+       }
+       onoff("IOTLB support", reg, PCI_SECURE_CAP_IOTLBSUP);
+       onoff("HyperTransport tunnel translation support", reg,
+           PCI_SECURE_CAP_HTTUNNEL);
+       onoff("Not present table entries cahced", reg, PCI_SECURE_CAP_NPCACHE);
+       onoff("IOMMU Extended Feature Register support", reg,
+           PCI_SECURE_CAP_EFRSUP);
+       onoff("IOMMU Miscellaneous Information Register 1", reg,
+           PCI_SECURE_CAP_EXT);
+       havemisc1 = reg & PCI_SECURE_CAP_EXT;
+       
+       reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)];
+       printf("    Base Address Low Register: 0x%08x\n", reg);
+       onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN);
+       reg2 = regs[o2i(capoff + PCI_SECURE_IOMMU_BAH)];
+       printf("    Base Address High Register: 0x%08x\n", reg2);
+       printf("      Base Address : 0x%016" PRIx64 "\n",
+           ((uint64_t)reg2 << 32)
+           | (reg & (PCI_SECURE_IOMMU_BAL_H | PCI_SECURE_IOMMU_BAL_L)));
+       
+       reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)];
+       printf("    IOMMU Range Register: 0x%08x\n", reg);
+       printf("      HyperTransport UnitID: 0x%02x\n",
+           (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_UNITID));
+       onoff("Range valid", reg, PCI_SECURE_IOMMU_RANGE_RNGVALID);
+       printf("      Device range bus number: 0x%02x\n",
+           (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_BUSNUM));
+       printf("      First device: 0x%04x\n",
+           (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_FIRSTDEV));
+       printf("      Last device: 0x%04x\n",
+           (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_LASTDEV));
+
+       reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC0)];
+       printf("    Miscellaneous Information Register 0: 0x%08x\n", reg);
+       printf("      MSI Message number: 0x%04x\n",
+           (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MSINUM));
+       val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_GVASIZE);
+       printf("      Guest Virtual Address size: ");
+       if (val == PCI_SECURE_IOMMU_MISC0_GVASIZE_48B)
+               printf("48bits\n");
+       else
+               printf("0x%x(unknown)\n", val);
+       val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_PASIZE);
+       printf("      Physical Address size: %dbits\n", val);
+       val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_VASIZE);
+       printf("      Virtual Address size: %dbits\n", val);
+       onoff("ATS response address range reserved", reg,
+           PCI_SECURE_IOMMU_MISC0_ATSRESV);
+       printf("      Peripheral Page Request MSI Message number: 0x%02x\n",
+           (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MISNPPR));
+
+       if (!havemisc1)
+               return;
+       
+       reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)];
+       printf("    Miscellaneous Information Register 1: 0x%08x\n", reg);
+       printf("      MSI Message number (GA): 0x%02x\n",
+           (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC1_MSINUM));
+}
 
 static void
 pci_print_pcie_L0s_latency(uint32_t val)
@@ -2352,7 +2435,7 @@
        { PCI_CAP_SUBVENDOR,    "Subsystem vendor ID",
          pci_conf_print_subsystem_cap },
        { PCI_CAP_AGP8,         "AGP 8x",       NULL },
-       { PCI_CAP_SECURE,       "Secure Device", NULL },
+       { PCI_CAP_SECURE,       "Secure Device", pci_conf_print_secure_cap },
        { PCI_CAP_PCIEXPRESS,   "PCI Express",  pci_conf_print_pcie_cap },
        { PCI_CAP_MSIX,         "MSI-X",        pci_conf_print_msix_cap },
        { PCI_CAP_SATA,         "SATA",         pci_conf_print_sata_cap },
diff -r 814627078988 -r 759e2223fd60 sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h      Tue Oct 10 03:05:29 2017 +0000
+++ b/sys/dev/pci/pcireg.h      Tue Oct 10 03:11:01 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pcireg.h,v 1.133 2017/10/05 06:14:30 msaitoh Exp $     */
+/*     $NetBSD: pcireg.h,v 1.134 2017/10/10 03:11:01 msaitoh Exp $     */
 
 /*
  * Copyright (c) 1995, 1996, 1999, 2000
@@ -900,8 +900,43 @@
 
 /*
  * Capability ID: 0x0f
- * Secure
+ * Secure Device
+ *
+ * Reference: AMD I/O Virtualization Technology(IOMMU) Specification (#48882)
+ * Revision 3.00.
  */
+#define PCI_SECURE_CAP        0x00 /* Capability Header */
+#define PCI_SECURE_CAP_TYPE    __BITS(18, 16)  /* Capability block type */
+#define PCI_SECURE_CAP_TYPE_IOMMU      0x3             /* IOMMU Cap */
+#define PCI_SECURE_CAP_REV     __BITS(23, 19)  /* Capability revision */
+#define PCI_SECURE_CAP_REV_IOMMU       0x01            /* IOMMU interface  */
+/* For IOMMU only */
+#define PCI_SECURE_CAP_IOTLBSUP        __BIT(24)       /* IOTLB */
+#define PCI_SECURE_CAP_HTTUNNEL        __BIT(25)       /* HT tunnel translation */
+#define PCI_SECURE_CAP_NPCACHE __BIT(26) /* Not present table entries cahced*/
+#define PCI_SECURE_CAP_EFRSUP  __BIT(27)       /* IOMMU Ext-Feature Reg */
+#define PCI_SECURE_CAP_EXT     __BIT(28)       /* IOMMU Misc Info Reg 1 */
+#define PCI_SECURE_IOMMU_BAL   0x04 /* Base Address Low */
+#define PCI_SECURE_IOMMU_BAL_EN                __BIT(0)        /* Enable */
+#define PCI_SECURE_IOMMU_BAL_L         __BITS(18, 14)  /* Base Addr [18:14] */
+#define PCI_SECURE_IOMMU_BAL_H         __BITS(31, 19)  /* Base Addr [31:19] */
+#define PCI_SECURE_IOMMU_BAH   0x08 /* Base Address High */
+#define PCI_SECURE_IOMMU_RANGE 0x0c /* IOMMU Range */
+#define PCI_SECURE_IOMMU_RANGE_UNITID  __BITS(4, 0)    /* HT UnitID */
+#define PCI_SECURE_IOMMU_RANGE_RNGVALID        __BIT(7)        /* Range valid */
+#define PCI_SECURE_IOMMU_RANGE_BUSNUM  __BITS(15, 8)   /* bus number */
+#define PCI_SECURE_IOMMU_RANGE_FIRSTDEV        __BITS(23, 16)  /* First device */
+#define PCI_SECURE_IOMMU_RANGE_LASTDEV __BITS(31, 24)  /* Last device */
+#define PCI_SECURE_IOMMU_MISC0 0x10 /* IOMMU Miscellaneous Information 0 */
+#define PCI_SECURE_IOMMU_MISC0_MSINUM  __BITS(4, 0)  /* MSI Message number */
+#define PCI_SECURE_IOMMU_MISC0_GVASIZE __BITS(7, 5) /* Guest Virtual Adr siz */
+#define PCI_SECURE_IOMMU_MISC0_GVASIZE_48B     0x2     /* 48bits */
+#define PCI_SECURE_IOMMU_MISC0_PASIZE  __BITS(14, 8) /* Physical Address siz */
+#define PCI_SECURE_IOMMU_MISC0_VASIZE  __BITS(21, 15)/* Virtual Address size */
+#define PCI_SECURE_IOMMU_MISC0_ATSRESV __BIT(22) /* ATS resp addr range rsvd */
+#define PCI_SECURE_IOMMU_MISC0_MISNPPR __BITS(31, 27)/* Periph Pg Rq MSI Msgn*/
+#define PCI_SECURE_IOMMU_MISC1 0x14 /* IOMMU Miscellaneous Information 1 */
+#define PCI_SECURE_IOMMU_MISC1_MSINUM __BITS(4, 0) /* MSI Messsage number(GA)*/
 
 /*
  * Capability ID: 0x10



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