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[src/trunk]: src/sys Add initial support for Rockchip RK3328 SoC.
details: https://anonhg.NetBSD.org/src/rev/d7e0e1b6eddd
branches: trunk
changeset: 362577:d7e0e1b6eddd
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sat Jun 16 00:19:04 2018 +0000
description:
Add initial support for Rockchip RK3328 SoC.
diffstat:
sys/arch/arm/rockchip/files.rockchip | 45 +++
sys/arch/arm/rockchip/rk3328_cru.c | 361 +++++++++++++++++++++++++++++
sys/arch/arm/rockchip/rk3328_cru.h | 213 +++++++++++++++++
sys/arch/arm/rockchip/rk3328_platform.h | 40 +++
sys/arch/arm/rockchip/rk_cru.c | 379 +++++++++++++++++++++++++++++++
sys/arch/arm/rockchip/rk_cru.h | 321 ++++++++++++++++++++++++++
sys/arch/arm/rockchip/rk_cru_arm.c | 139 +++++++++++
sys/arch/arm/rockchip/rk_cru_composite.c | 178 ++++++++++++++
sys/arch/arm/rockchip/rk_cru_gate.c | 64 +++++
sys/arch/arm/rockchip/rk_cru_mux.c | 84 ++++++
sys/arch/arm/rockchip/rk_cru_pll.c | 170 +++++++++++++
sys/arch/arm/rockchip/rk_gmac.c | 323 ++++++++++++++++++++++++++
sys/arch/arm/rockchip/rk_gpio.c | 323 ++++++++++++++++++++++++++
sys/arch/arm/rockchip/rk_iomux.c | 329 ++++++++++++++++++++++++++
sys/arch/arm/rockchip/rk_platform.c | 160 +++++++++++++
sys/arch/arm/rockchip/rk_usb.c | 316 +++++++++++++++++++++++++
sys/arch/evbarm/conf/GENERIC64 | 17 +-
sys/arch/evbarm/conf/files.generic64 | 3 +-
sys/dev/fdt/dwc2_fdt.c | 207 ++++++++++++++++
sys/dev/fdt/dwcmmc_fdt.c | 176 ++++++++++++++
sys/dev/fdt/files.fdt | 10 +-
21 files changed, 3854 insertions(+), 4 deletions(-)
diffs (truncated from 4034 to 300 lines):
diff -r d748fb6d9379 -r d7e0e1b6eddd sys/arch/arm/rockchip/files.rockchip
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/rockchip/files.rockchip Sat Jun 16 00:19:04 2018 +0000
@@ -0,0 +1,45 @@
+# $NetBSD: files.rockchip,v 1.13 2018/06/16 00:19:04 jmcneill Exp $
+#
+# Configuration info for Rockchip family SoCs
+#
+#
+
+file arch/arm/rockchip/rk_platform.c soc_rockchip
+
+# Clock and reset unit (CRU)
+device rkcru: rk_cru
+file arch/arm/rockchip/rk_cru.c rk_cru
+file arch/arm/rockchip/rk_cru_arm.c rk_cru
+file arch/arm/rockchip/rk_cru_composite.c rk_cru
+file arch/arm/rockchip/rk_cru_gate.c rk_cru
+file arch/arm/rockchip/rk_cru_mux.c rk_cru
+file arch/arm/rockchip/rk_cru_pll.c rk_cru
+
+# RK3328 clock and reset unit
+attach rkcru at fdt with rk3328_cru
+file arch/arm/rockchip/rk3328_cru.c rk3328_cru & soc_rk3328
+
+# IOMUX control
+device rkiomux { }
+attach rkiomux at fdt with rk_iomux
+file arch/arm/rockchip/rk_iomux.c rk_iomux
+
+# GPIO
+device rkgpio: gpiobus
+attach rkgpio at rkiomux with rk_gpio
+file arch/arm/rockchip/rk_gpio.c rk_gpio
+
+# USB PHY
+device rkusb { }
+attach rkusb at fdt with rk_usb
+device rkusbphy
+attach rkusbphy at rkusb with rk_usbphy
+file arch/arm/rockchip/rk_usb.c rk_usb | rk_usbphy
+
+# GMAC
+attach awge at fdt with rk_gmac
+file arch/arm/rockchip/rk_gmac.c rk_gmac
+
+# SOC parameters
+defflag opt_soc.h SOC_ROCKCHIP
+defflag opt_soc.h SOC_RK3328: SOC_ROCKCHIP
diff -r d748fb6d9379 -r d7e0e1b6eddd sys/arch/arm/rockchip/rk3328_cru.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/rockchip/rk3328_cru.c Sat Jun 16 00:19:04 2018 +0000
@@ -0,0 +1,361 @@
+/* $NetBSD: rk3328_cru.c,v 1.1 2018/06/16 00:19:04 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2018 Jared McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: rk3328_cru.c,v 1.1 2018/06/16 00:19:04 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/rockchip/rk_cru.h>
+#include <arm/rockchip/rk3328_cru.h>
+
+static int rk3328_cru_match(device_t, cfdata_t, void *);
+static void rk3328_cru_attach(device_t, device_t, void *);
+
+static const char * const compatible[] = {
+ "rockchip,rk3328-cru",
+ NULL
+};
+
+CFATTACH_DECL_NEW(rk3328_cru, sizeof(struct rk_cru_softc),
+ rk3328_cru_match, rk3328_cru_attach, NULL, NULL);
+
+static const struct rk_cru_pll_rate pll_rates[] = {
+ RK_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+ RK_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
+ RK_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
+ RK_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
+ RK_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
+ RK_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
+ RK_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
+ RK_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
+ RK_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
+ RK_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
+ RK_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
+ RK_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
+ RK_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
+ RK_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
+ RK_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
+ RK_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
+ RK_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
+ RK_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
+ RK_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
+ RK_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
+ RK_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
+ RK_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
+ RK_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
+ RK_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
+ RK_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
+ RK_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
+ RK_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
+ RK_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
+ RK_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
+ RK_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
+ RK_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
+ RK_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
+ RK_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
+ RK_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
+ RK_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
+ RK_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
+ RK_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
+ RK_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
+ RK_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
+ RK_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
+ RK_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
+ RK_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
+};
+
+static const struct rk_cru_pll_rate pll_frac_rates[] = {
+ RK_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134217),
+ RK_PLL_RATE( 983040000, 24, 983, 1, 1, 0, 671088),
+ RK_PLL_RATE( 491520000, 24, 983, 2, 1, 0, 671088),
+ RK_PLL_RATE( 61440000, 6, 215, 7, 2, 0, 671088),
+ RK_PLL_RATE( 56448000, 12, 451, 4, 4, 0, 9797894),
+ RK_PLL_RATE( 40960000, 12, 409, 4, 5, 0, 10066329),
+};
+
+static const struct rk_cru_pll_rate pll_norates[] = {
+};
+
+static const struct rk_cru_arm_rate armclk_rates[] = {
+ RK_ARM_RATE(1296000000, 1),
+ RK_ARM_RATE(1200000000, 1),
+ RK_ARM_RATE(1104000000, 1),
+ RK_ARM_RATE(1008000000, 1),
+ RK_ARM_RATE( 912000000, 1),
+ RK_ARM_RATE( 816000000, 1),
+ RK_ARM_RATE( 696000000, 1),
+ RK_ARM_RATE( 600000000, 1),
+ RK_ARM_RATE( 408000000, 1),
+ RK_ARM_RATE( 312000000, 1),
+ RK_ARM_RATE( 216000000, 1),
+ RK_ARM_RATE( 96000000, 1),
+};
+
+static const char * armclk_parents[] = { "apll", "gpll", "dpll", "npll" };
+static const char * aclk_bus_pre_parents[] = { "cpll", "gpll", "hdmiphy" };
+static const char * hclk_bus_pre_parents[] = { "aclk_bus_pre" };
+static const char * aclk_peri_pre_parents[] = { "cpll", "gpll", "hdmiphy" };
+static const char * mmc_parents[] = { "cpll", "gpll", "xin24m", "usb480m" };
+static const char * phclk_peri_parents[] = { "aclk_peri_pre" };
+static const char * mux_usb480m_parents[] = { "usb480m_phy", "xin24m" };
+static const char * mux_uart0_parents[] = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
+static const char * mux_uart1_parents[] = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
+static const char * mux_uart2_parents[] = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
+static const char * mux_mac2io_src_parents[] = { "clk_mac2io_src", "gmac_clkin" };
+static const char * mux_mac2io_ext_parents[] = { "clk_mac2io", "gmac_clkin" };
+static const char * mux_2plls_parents[] = { "cpll", "gpll" };
+static const char * mux_2plls_hdmiphy_parents[] = { "cpll", "gpll", "dummy_hdmiphy" };
+static const char * comp_uart_parents[] = { "cpll", "gpll", "usb480m" };
+static const char * pclk_gmac_parents[] = { "aclk_gmac" };
+
+static struct rk_cru_clk rk3328_cru_clks[] = {
+ RK_PLL(RK3328_PLL_APLL, "apll", "xin24m",
+ 0x0000, /* con_base */
+ 0x80, /* mode_reg */
+ __BIT(0), /* mode_mask */
+ __BIT(4), /* lock_mask */
+ pll_frac_rates),
+ RK_PLL(RK3328_PLL_DPLL, "dpll", "xin24m",
+ 0x0020, /* con_base */
+ 0x80, /* mode_reg */
+ __BIT(4), /* mode_mask */
+ __BIT(3), /* lock_mask */
+ pll_norates),
+ RK_PLL(RK3328_PLL_CPLL, "cpll", "xin24m",
+ 0x0040, /* con_base */
+ 0x80, /* mode_reg */
+ __BIT(8), /* mode_mask */
+ __BIT(2), /* lock_mask */
+ pll_rates),
+ RK_PLL(RK3328_PLL_GPLL, "gpll", "xin24m",
+ 0x0060, /* con_base */
+ 0x80, /* mode_reg */
+ __BIT(12), /* mode_mask */
+ __BIT(1), /* lock_mask */
+ pll_frac_rates),
+ RK_PLL(RK3328_PLL_NPLL, "npll", "xin24m",
+ 0x00a0, /* con_base */
+ 0x80, /* mode_reg */
+ __BIT(1), /* mode_mask */
+ __BIT(0), /* lock_mask */
+ pll_rates),
+
+ RK_ARM(RK3328_ARMCLK, "armclk", armclk_parents,
+ 0x0100, /* reg */
+ __BITS(7,6), 3, 0, /* mux_mask, mux_main, mux_alt */
+ __BITS(4,0), /* div_mask */
+ armclk_rates),
+
+ RK_COMPOSITE(RK3328_ACLK_BUS_PRE, "aclk_bus_pre", aclk_bus_pre_parents,
+ 0x0100, /* muxdiv_reg */
+ __BITS(14,13), /* mux_mask */
+ __BITS(12,8), /* div_mask */
+ 0x0220, /* gate_reg */
+ __BIT(0), /* gate_mask */
+ 0),
+ RK_COMPOSITE(RK3328_HCLK_BUS_PRE, "hclk_bus_pre", hclk_bus_pre_parents,
+ 0x0104, /* muxdiv_reg */
+ 0, /* mux_mask */
+ __BITS(9,8), /* div_mask */
+ 0x0220, /* gate_reg */
+ __BIT(1), /* gate_mask */
+ 0),
+ RK_COMPOSITE(RK3328_PCLK_BUS_PRE, "pclk_bus_pre", hclk_bus_pre_parents,
+ 0x0104, /* muxdiv_reg */
+ 0, /* mux_mask */
+ __BITS(14,12), /* div_mask */
+ 0x0220, /* gate_reg */
+ __BIT(2), /* gate_mask */
+ 0),
+ RK_COMPOSITE(RK3328_ACLK_PERI_PRE, "aclk_peri_pre", aclk_peri_pre_parents,
+ 0x0170, /* muxdiv_reg */
+ __BITS(7,6), /* mux_mask */
+ __BITS(4,0), /* div_mask */
+ 0, 0, /* gate_reg, gate_mask */
+ 0),
+ RK_COMPOSITE(RK3328_PCLK_PERI, "pclk_peri", phclk_peri_parents,
+ 0x0174, /* muxdiv_reg */
+ 0, /* mux_mask */
+ __BITS(6,4), /* div_mask */
+ 0x0228, /* gate_reg */
+ __BIT(2), /* gate_mask */
+ 0),
+ RK_COMPOSITE(RK3328_HCLK_PERI, "hclk_peri", phclk_peri_parents,
+ 0x0174, /* muxdiv_reg */
+ 0, /* mux_mask */
+ __BITS(1,0), /* div_mask */
+ 0x0228, /* gate_reg */
+ __BIT(1), /* gate_mask */
+ 0),
+ RK_COMPOSITE(RK3328_SCLK_SDMMC, "clk_sdmmc", mmc_parents,
+ 0x0178, /* muxdiv_reg */
+ __BITS(9,8), /* mux_mask */
+ __BITS(7,0), /* div_mask */
+ 0x0210, /* gate_reg */
+ __BIT(3), /* gate_mask */
+ RK_COMPOSITE_ROUND_DOWN),
+ RK_COMPOSITE(RK3328_SCLK_SDIO, "clk_sdio", mmc_parents,
+ 0x0180, /* muxdiv_reg */
+ __BITS(9,8), /* mux_mask */
+ __BITS(7,0), /* div_mask */
+ 0x0210, /* gate_reg */
+ __BIT(5), /* gate_mask */
+ RK_COMPOSITE_ROUND_DOWN),
+ RK_COMPOSITE(RK3328_SCLK_EMMC, "clk_emmc", mmc_parents,
+ 0x017c, /* muxdiv_reg */
+ __BITS(9,8), /* mux_mask */
+ __BITS(7,0), /* div_mask */
+ 0x0210, /* gate_reg */
+ __BIT(4), /* gate_mask */
+ RK_COMPOSITE_ROUND_DOWN),
+ RK_COMPOSITE(0, "clk_uart0_div", comp_uart_parents,
+ 0x0138, /* muxdiv_reg */
+ __BITS(13,12), /* mux_mask */
+ __BITS(6,0), /* div_mask */
+ 0x0204, /* gate_reg */
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