[src/trunk]: src/sys/arch/mips/mips don't blindly zero STATUS in order to dis...

[macallan <macallan%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/d56cb61f351f
branches:  trunk
changeset: 348976:d56cb61f351f
user:      macallan <macallan%NetBSD.org@localhost>
date:      Fri Nov 18 13:50:36 2016 +0000

description:
don't blindly zero STATUS in order to disable interrupts, instead take care
to preserve bits like KX in case we catch an interrupt between mtc0 and the
write actually taking effect
now n32 kernels on my O2 are (mostly) stable again
ok skrll@

diffstat:

 sys/arch/mips/mips/spl.S |  37 +++++++++++++++++++++++++++++++------
 1 files changed, 31 insertions(+), 6 deletions(-)

diffs (88 lines):

diff -r 74e47128e41a -r d56cb61f351f sys/arch/mips/mips/spl.S
--- a/sys/arch/mips/mips/spl.S  Fri Nov 18 12:42:10 2016 +0000
+++ b/sys/arch/mips/mips/spl.S  Fri Nov 18 13:50:36 2016 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: spl.S,v 1.14 2016/11/11 16:49:30 maya Exp $    */
+/*     $NetBSD: spl.S,v 1.15 2016/11/18 13:50:36 macallan Exp $        */
 
 /*-
  * Copyright (c) 2009, 2010 The NetBSD Foundation, Inc.
@@ -38,7 +38,7 @@
 #include <mips/asm.h>
 #include <mips/cpuregs.h>
 
-RCSID("$NetBSD: spl.S,v 1.14 2016/11/11 16:49:30 maya Exp $")
+RCSID("$NetBSD: spl.S,v 1.15 2016/11/18 13:50:36 macallan Exp $")
 
 #include "assym.h"
 
@@ -80,8 +80,9 @@
        or      v1, MIPS_INT_MASK               # enable all interrupts
        xor     a0, v1                          # disable ipl's masked bits
        DYNAMIC_STATUS_MASK(a0,v0)              # machine dependent masking
-#if !defined(__mips_o32) && defined(MULTIPROCESSOR)
-       li      v1, MIPS3_SR_KX                 # keep 64-bit addressing on
+#if !defined(__mips_o32)
+       or      v1, MIPS_SR_INT_IE              #
+       xor     v1, MIPS_SR_INT_IE              # clear interrupt enable bit
        mtc0    v1, MIPS_COP_0_STATUS           ## disable interrupts
 #else
        mtc0    zero, MIPS_COP_0_STATUS         ## disable interrupts
@@ -136,7 +137,13 @@
        xor     a1, MIPS_INT_MASK               # invert SR bits
        or      v1, a1                          # set any bits for this IPL
        DYNAMIC_STATUS_MASK(v1,t0)              # machine dependent masking
+#if !defined(__mips_o32)
+       or      v0, v1, MIPS_SR_INT_IE          #
+       xor     v0, MIPS_SR_INT_IE              # clear interrupt enable bit
+       mtc0    v0, MIPS_COP_0_STATUS           ## disable interrupts
+#else
        mtc0    zero, MIPS_COP_0_STATUS         ## disable interrupts
+#endif
        COP0_SYNC
        INT_S   a0, CPU_INFO_CPL(a3)            ## save IPL in cpu_info (KSEG0)
        mtc0    v1, MIPS_COP_0_STATUS           ## store back
@@ -170,7 +177,13 @@
        MFC0_HAZARD                             # load delay
        or      v0, a0, v1
        DYNAMIC_STATUS_MASK(v0,t0)              # machine dependent masking
+#if !defined(__mips_o32)
+       or      v1, v0, MIPS_SR_INT_IE          #
+       xor     v1, MIPS_SR_INT_IE              # clear interrupt enable bit
+       mtc0    v1, MIPS_COP_0_STATUS           ## disable interrupts
+#else
        mtc0    zero, MIPS_COP_0_STATUS         ## disable interrupts
+#endif
        COP0_SYNC
 #if IPL_NONE == 0
        INT_S   zero, CPU_INFO_CPL(a3)          ## set ipl to 0
@@ -183,7 +196,13 @@
 
 STATIC_LEAF(_splsw_setsoftintr)
        mfc0    v1, MIPS_COP_0_STATUS           # save status register
-       mtc0    zero, MIPS_COP_0_STATUS         # disable interrupts (2 cycles)
+#if !defined(__mips_o32)
+       or      v0, v1, MIPS_SR_INT_IE          #
+       xor     v0, MIPS_SR_INT_IE              # clear interrupt enable bit
+       mtc0    v0, MIPS_COP_0_STATUS           ## disable interrupts
+#else
+       mtc0    zero, MIPS_COP_0_STATUS         ## disable interrupts
+#endif
        COP0_SYNC
        mfc0    v0, MIPS_COP_0_CAUSE            # fetch cause register
        MFC0_HAZARD                             # load delay
@@ -196,7 +215,13 @@
 
 STATIC_LEAF(_splsw_clrsoftintr)
        mfc0    v1, MIPS_COP_0_STATUS           # save status register
-       mtc0    zero, MIPS_COP_0_STATUS         # disable interrupts (2 cycles)
+#if !defined(__mips_o32)
+       or      v0, v1, MIPS_SR_INT_IE          #
+       xor     v0, MIPS_SR_INT_IE              # clear interrupt enable bit
+       mtc0    v0, MIPS_COP_0_STATUS           ## disable interrupts
+#else
+       mtc0    zero, MIPS_COP_0_STATUS         ## disable interrupts
+#endif
        COP0_SYNC
        mfc0    v0, MIPS_COP_0_CAUSE            # fetch cause register
        nor     a0, zero, a0                    # bitwise inverse of A0