[src/trunk]: src/sys/arch/arm/nvidia More defines

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/37e1b5f7b7f2
branches:  trunk
changeset: 339462:37e1b5f7b7f2
user:      skrll <skrll%NetBSD.org@localhost>
date:      Thu Jul 23 15:08:19 2015 +0000

description:
More defines

diffstat:

 sys/arch/arm/nvidia/tegra_dcreg.h   |  12 ++++++++++--
 sys/arch/arm/nvidia/tegra_hdmireg.h |  10 +++++++++-
 2 files changed, 19 insertions(+), 3 deletions(-)

diffs (56 lines):

diff -r 2e6ce5861957 -r 37e1b5f7b7f2 sys/arch/arm/nvidia/tegra_dcreg.h
--- a/sys/arch/arm/nvidia/tegra_dcreg.h Thu Jul 23 15:07:31 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_dcreg.h Thu Jul 23 15:08:19 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_dcreg.h,v 1.2 2015/07/23 14:31:05 jmcneill Exp $ */
+/* $NetBSD: tegra_dcreg.h,v 1.3 2015/07/23 15:08:19 skrll Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -139,12 +139,20 @@
  * Display DISP registers
  */
 #define DC_DISP_DISP_SIGNAL_OPTIONS0_REG               0x1000
+#define DC_DISP_DISP_SIGNAL_OPTIONS0_M1_ENABLE         __BIT(26)
+#define DC_DISP_DISP_SIGNAL_OPTIONS0_M0_ENABLE         __BIT(24)
+#define DC_DISP_DISP_SIGNAL_OPTIONS0_V_PULSE3_ENABLE   __BIT(20)
+#define DC_DISP_DISP_SIGNAL_OPTIONS0_V_PULSE2_ENABLE   __BIT(19)
+#define DC_DISP_DISP_SIGNAL_OPTIONS0_V_PULSE1_ENABLE   __BIT(18)
+#define DC_DISP_DISP_SIGNAL_OPTIONS0_V_PULSE0_ENABLE   __BIT(16)
 #define DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE2_ENABLE   __BIT(12)
+#define DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE1_ENABLE   __BIT(10)
+#define DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE0_ENABLE   __BIT(8)
 
 #define DC_DISP_DISP_WIN_OPTIONS_REG                   0x1008
 #define DC_DISP_DISP_WIN_OPTIONS_HDMI_ENABLE           __BIT(30)
 #define DC_DISP_DISP_WIN_OPTIONS_DSI_ENABLE            __BIT(29)
-#define DC_DISP_DISP_WIN_OPTIONS_SOR_ENABLE            __BIT(28)
+#define DC_DISP_DISP_WIN_OPTIONS_SOR_ENABLE            __BIT(25)
 #define DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE         __BIT(16)
 
 #define DC_DISP_DISP_TIMING_OPTIONS_REG                        0x1014
diff -r 2e6ce5861957 -r 37e1b5f7b7f2 sys/arch/arm/nvidia/tegra_hdmireg.h
--- a/sys/arch/arm/nvidia/tegra_hdmireg.h       Thu Jul 23 15:07:31 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_hdmireg.h       Thu Jul 23 15:08:19 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_hdmireg.h,v 1.2 2015/07/23 14:31:05 jmcneill Exp $ */
+/* $NetBSD: tegra_hdmireg.h,v 1.3 2015/07/23 15:08:19 skrll Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -216,7 +216,15 @@
 #define HDMI_NV_PDISP_SOR_CRCA_REG                             0x170
 #define HDMI_NV_PDISP_SOR_CRCB_REG                             0x174
 #define HDMI_NV_PDISP_SOR_BLANK_REG                            0x178
+
 #define HDMI_NV_PDISP_SOR_SEQ_CTL_REG                          0x17c
+#define HDMI_NV_PDISP_SOR_SEQ_CTL_SWITCH                       __BIT(30)
+#define HDMI_NV_PDISP_SOR_SEQ_CTL_STATUS                       __BIT(28)
+#define HDMI_NV_PDISP_SOR_SEQ_CTL_PC                           __BITS(19,16)
+#define HDMI_NV_PDISP_SOR_SEQ_CTL_PD_PC_ALT                    __BITS(15,12)
+#define HDMI_NV_PDISP_SOR_SEQ_CTL_PD_PC                                __BITS(11,8)
+#define HDMI_NV_PDISP_SOR_SEQ_CTL_PU_PC_ALT                    __BITS(7,4)
+#define HDMI_NV_PDISP_SOR_SEQ_CTL_PU_PC                                __BITS(3,0)
 
 #define HDMI_NV_PDISP_SOR_SEQ_INST0_REG                                0x180
 #define HDMI_NV_PDISP_SOR_SEQ_INST1_REG                                0x184