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[src/trunk]: src/sys/arch Add support imx6 PCIe controller.
details: https://anonhg.NetBSD.org/src/rev/19646c835418
branches: trunk
changeset: 349115:19646c835418
user: hkenken <hkenken%NetBSD.org@localhost>
date: Thu Nov 24 12:06:43 2016 +0000
description:
Add support imx6 PCIe controller.
diffstat:
sys/arch/arm/imx/files.imx6 | 8 +-
sys/arch/arm/imx/imx6_pcie.c | 942 ++++++++++++++++++++++++++++
sys/arch/arm/imx/imx6_pciereg.h | 295 ++++++++
sys/arch/evbarm/conf/HUMMINGBOARD | 158 ++++
sys/arch/evbarm/conf/std.nitrogen6 | 3 +-
sys/arch/evbarm/nitrogen6/nitrogen6_iomux.c | 64 +-
6 files changed, 1457 insertions(+), 13 deletions(-)
diffs (truncated from 1583 to 300 lines):
diff -r 17a925554bb1 -r 19646c835418 sys/arch/arm/imx/files.imx6
--- a/sys/arch/arm/imx/files.imx6 Thu Nov 24 11:54:57 2016 +0000
+++ b/sys/arch/arm/imx/files.imx6 Thu Nov 24 12:06:43 2016 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.imx6,v 1.7 2016/05/17 06:44:45 ryo Exp $
+# $NetBSD: files.imx6,v 1.8 2016/11/24 12:06:43 hkenken Exp $
#
# Configuration info for the Freescale i.MX6
#
@@ -26,6 +26,11 @@
attach axi at mainbus
file arch/arm/imx/imx6_axi.c axi
+# iMX6 PCIe
+device imxpcie: pcibus
+attach imxpcie at axi
+file arch/arm/imx/imx6_pcie.c imxpcie
+
# iMX6 Clock Control Module
device imxccm
attach imxccm at axi
@@ -101,4 +106,3 @@
attach imxsnvs at axi
file arch/arm/imx/imxsnvs.c imxsnvs
file arch/arm/imx/imx6_snvs.c imxsnvs
-
diff -r 17a925554bb1 -r 19646c835418 sys/arch/arm/imx/imx6_pcie.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/imx6_pcie.c Thu Nov 24 12:06:43 2016 +0000
@@ -0,0 +1,942 @@
+/* $NetBSD: imx6_pcie.c,v 1.1 2016/11/24 12:06:43 hkenken Exp $ */
+
+/*
+ * Copyright (c) 2016 Genetec Corporation. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * i.MX6 On-Chip PCI Express Controller
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: imx6_pcie.c,v 1.1 2016/11/24 12:06:43 hkenken Exp $");
+
+#include "opt_pci.h"
+#include "opt_imx6pcie.h"
+
+#include "pci.h"
+#include "imxgpio.h"
+#include "locators.h"
+
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/extent.h>
+#include <sys/queue.h>
+#include <sys/mutex.h>
+#include <sys/kmem.h>
+#include <sys/gpio.h>
+
+#include <machine/frame.h>
+#include <arm/cpufunc.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pciconf.h>
+
+#include <arm/imx/imxgpioreg.h>
+#include <arm/imx/imxgpiovar.h>
+#include <arm/imx/imx6var.h>
+#include <arm/imx/imx6_reg.h>
+#include <arm/imx/imx6_pciereg.h>
+#include <arm/imx/imx6_iomuxreg.h>
+#include <arm/imx/imx6_ccmreg.h>
+#include <arm/imx/imx6_ccmvar.h>
+
+static int imx6pcie_match(device_t, cfdata_t, void *);
+static void imx6pcie_attach(device_t, device_t, void *);
+
+#define IMX6_PCIE_MEM_BASE 0x01000000
+#define IMX6_PCIE_MEM_SIZE 0x00f00000 /* 15MB */
+#define IMX6_PCIE_ROOT_BASE 0x01f00000
+#define IMX6_PCIE_ROOT_SIZE 0x00080000 /* 512KB */
+#define IMX6_PCIE_IO_BASE 0x01f80000
+#define IMX6_PCIE_IO_SIZE 0x00010000 /* 64KB */
+
+struct imx6pcie_ih {
+ int (*ih_handler)(void *);
+ void *ih_arg;
+ int ih_ipl;
+ TAILQ_ENTRY(imx6pcie_ih) ih_entry;
+};
+
+struct imx6pcie_softc {
+ device_t sc_dev;
+
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_ioh;
+ bus_space_handle_t sc_root_ioh;
+ bus_dma_tag_t sc_dmat;
+
+ struct arm32_pci_chipset sc_pc;
+
+ TAILQ_HEAD(, imx6pcie_ih) sc_intrs;
+
+ void *sc_ih;
+ kmutex_t sc_lock;
+ u_int sc_intrgen;
+
+ int32_t sc_gpio_reset;
+ int32_t sc_gpio_reset_active;
+ int32_t sc_gpio_pwren;
+ int32_t sc_gpio_pwren_active;
+};
+
+#define PCIE_CONF_LOCK(s) (s) = disable_interrupts(I32_bit)
+#define PCIE_CONF_UNLOCK(s) restore_interrupts((s))
+
+#define PCIE_READ(sc, reg) \
+ bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, reg)
+#define PCIE_WRITE(sc, reg, val) \
+ bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, reg, val)
+
+static int imx6pcie_intr(void *);
+static void imx6pcie_init(pci_chipset_tag_t, void *);
+static void imx6pcie_setup(struct imx6pcie_softc * const);
+
+static void imx6pcie_attach_hook(device_t, device_t,
+ struct pcibus_attach_args *);
+static int imx6pcie_bus_maxdevs(void *, int);
+static pcitag_t imx6pcie_make_tag(void *, int, int, int);
+static void imx6pcie_decompose_tag(void *, pcitag_t, int *, int *, int *);
+static pcireg_t imx6pcie_conf_read(void *, pcitag_t, int);
+static void imx6pcie_conf_write(void *, pcitag_t, int, pcireg_t);
+#ifdef __HAVE_PCI_CONF_HOOK
+static int imx6pcie_conf_hook(void *, int, int, int, pcireg_t);
+#endif
+static void imx6pcie_conf_interrupt(void *, int, int, int, int, int *);
+
+static int imx6pcie_intr_map(const struct pci_attach_args *,
+ pci_intr_handle_t *);
+static const char *imx6pcie_intr_string(void *, pci_intr_handle_t,
+ char *, size_t);
+const struct evcnt *imx6pcie_intr_evcnt(void *, pci_intr_handle_t);
+static void * imx6pcie_intr_establish(void *, pci_intr_handle_t,
+ int, int (*)(void *), void *);
+static void imx6pcie_intr_disestablish(void *, void *);
+
+CFATTACH_DECL_NEW(imxpcie, sizeof(struct imx6pcie_softc),
+ imx6pcie_match, imx6pcie_attach, NULL, NULL);
+
+static void
+imx6pcie_clock_enable(struct imx6pcie_softc *sc)
+{
+ uint32_t v;
+
+ v = imx6_ccm_read(CCM_ANALOG_MISC1);
+ v &= ~CCM_ANALOG_MISC1_LVDS_CLK1_IBEN;
+ v &= ~CCM_ANALOG_MISC1_LVDS_CLK1_SRC;
+ v |= CCM_ANALOG_MISC1_LVDS_CLK1_OBEN;
+ v |= CCM_ANALOG_MISC1_LVDS_CLK1_SRC_SATA;
+ imx6_ccm_write(CCM_ANALOG_MISC1, v);
+
+ /* select PCIe clock source from axi */
+ v = imx6_ccm_read(CCM_CBCMR);
+ v &= ~CCM_CBCMR_PCIE_AXI_CLK_SEL;
+ imx6_ccm_write(CCM_CBCMR, v);
+
+ /* AHCISATA clock enable */
+ v = imx6_ccm_read(CCM_CCGR5);
+ v |= CCM_CCGR5_100M_CLK_ENABLE(3);
+ imx6_ccm_write(CCM_CCGR5, v);
+
+ /* PCIe clock enable */
+ v = imx6_ccm_read(CCM_CCGR4);
+ v |= CCM_CCGR4_125M_ROOT_ENABLE(3);
+ imx6_ccm_write(CCM_CCGR4, v);
+
+ /* PLL power up */
+ if (imx6_pll_power(CCM_ANALOG_PLL_ENET, 1,
+ CCM_ANALOG_PLL_ENET_ENABLE_125M |
+ CCM_ANALOG_PLL_ENET_ENABLE_100M) != 0) {
+ aprint_error_dev(sc->sc_dev,
+ "couldn't enable CCM_ANALOG_PLL_ENET\n");
+ return;
+ }
+}
+
+static int
+imx6pcie_init_phy(struct imx6pcie_softc *sc)
+{
+ uint32_t v;
+
+ /* initialize IOMUX */
+ v = iomux_read(IOMUX_GPR12);
+ v &= ~IOMUX_GPR12_APP_LTSSM_ENABLE;
+ iomux_write(IOMUX_GPR12, v);
+
+ v &= ~IOMUX_GPR12_DEVICE_TYPE;
+ v |= IOMUX_GPR12_DEVICE_TYPE_PCIE_RC;
+ iomux_write(IOMUX_GPR12, v);
+
+ v &= ~IOMUX_GPR12_LOS_LEVEL;
+ v |= __SHIFTIN(9, IOMUX_GPR12_LOS_LEVEL);
+ iomux_write(IOMUX_GPR12, v);
+
+ v = 0;
+ v |= __SHIFTIN(0x7f, IOMUX_GPR8_PCS_TX_SWING_LOW);
+ v |= __SHIFTIN(0x7f, IOMUX_GPR8_PCS_TX_SWING_FULL);
+ v |= __SHIFTIN(20, IOMUX_GPR8_PCS_TX_DEEMPH_GEN2_6DB);
+ v |= __SHIFTIN(0, IOMUX_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB);
+ v |= __SHIFTIN(0, IOMUX_GPR8_PCS_TX_DEEMPH_GEN1);
+ iomux_write(IOMUX_GPR8, v);
+
+ return 0;
+}
+
+static int
+imx6pcie_phy_wait_ack(struct imx6pcie_softc *sc, int ack)
+{
+ uint32_t v;
+ int timeout;
+
+ for (timeout = 10; timeout > 0; --timeout) {
+ v = PCIE_READ(sc, PCIE_PL_PHY_STATUS);
+ if (!!(v & PCIE_PL_PHY_STATUS_ACK) == !!ack)
+ return 0;
+ delay(1);
+ }
+
+ return -1;
+}
+
+static int
+imx6pcie_phy_addr(struct imx6pcie_softc *sc, uint32_t addr)
+{
+ uint32_t v;
+
+ v = __SHIFTIN(addr, PCIE_PL_PHY_CTRL_DATA);
+ PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, v);
+
+ v |= PCIE_PL_PHY_CTRL_CAP_ADR;
+ PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, v);
+
+ if (imx6pcie_phy_wait_ack(sc, 1))
+ return -1;
+
+ v = __SHIFTIN(addr, PCIE_PL_PHY_CTRL_DATA);
+ PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, v);
+
+ if (imx6pcie_phy_wait_ack(sc, 0))
+ return -1;
+
+ return 0;
+}
+
+static int
+imx6pcie_phy_write(struct imx6pcie_softc *sc, uint32_t addr, uint16_t data)
+{
+ /* write address */
+ if (imx6pcie_phy_addr(sc, addr) != 0)
+ return -1;
+
+ /* store data */
+ PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, __SHIFTIN(data, PCIE_PL_PHY_CTRL_DATA));
+
+ /* assert CAP_DAT and wait ack */
+ PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, __SHIFTIN(data, PCIE_PL_PHY_CTRL_DATA) | PCIE_PL_PHY_CTRL_CAP_DAT);
+ if (imx6pcie_phy_wait_ack(sc, 1))
+ return -1;
+
+ /* deassert CAP_DAT and wait ack */
+ PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, __SHIFTIN(data, PCIE_PL_PHY_CTRL_DATA));
+ if (imx6pcie_phy_wait_ack(sc, 0))
+ return -1;
+
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