[src/trunk]: src/sys/arch/arm/cortex Call armv7_dcache_l1inv_all in mpstart

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/6a03de0c6b24
branches:  trunk
changeset: 338584:6a03de0c6b24
user:      matt <matt%NetBSD.org@localhost>
date:      Sat May 30 21:44:38 2015 +0000

description:
Call armv7_dcache_l1inv_all in mpstart
Make sure ACTRL<31> is set on A15 with 3+ cores.

diffstat:

 sys/arch/arm/cortex/a9_mpsubr.S |  42 ++++++++++++++++++++++++++++++----------
 1 files changed, 31 insertions(+), 11 deletions(-)

diffs (72 lines):

diff -r 02876e99689d -r 6a03de0c6b24 sys/arch/arm/cortex/a9_mpsubr.S
--- a/sys/arch/arm/cortex/a9_mpsubr.S   Sat May 30 21:25:22 2015 +0000
+++ b/sys/arch/arm/cortex/a9_mpsubr.S   Sat May 30 21:44:38 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: a9_mpsubr.S,v 1.39 2015/05/28 02:23:18 matt Exp $      */
+/*     $NetBSD: a9_mpsubr.S,v 1.40 2015/05/30 21:44:38 matt Exp $      */
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -339,14 +339,30 @@
         mov    r0, #0
         msr    spsr_sxc, r0                    // set SPSR[23:8] to known value
 
+#if 0
+       mrc     p14, 0, r0, c0, c0, 0           // MIDR read
+       ufbx    r0, r0, #4, #4                  // extract cortex part.
+       mov     r5, #1
+       lsl     r5, r5, r0
+#endif
+
        XPUTC(#'@')
 #if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA17)
        //
-       // If SMP is already enabled, don't do anything.
+       // If SMP is already enabled, don't do anything (maybe).
        //
        mrc     p15, 0, r0, c1, c0, 1           // ACTLR read
-       tst     r0, #CORTEXA9_AUXCTL_SMP        // test SMP
-       bxne    r10                             // return if set
+       orr     r1, r0, #CORTEXA9_AUXCTL_SMP    // test SMP
+#if defined(CPU_CORTEXA15)
+       // The A15 requires snoop-delayed exclusive handling to be set
+       // if there are 3 or more CPUs.
+       mrc     p15, 1, r2, c9, c0, 2           // L2CTRL read
+       ubfx    r2, r2, #25, #1                 // bit 25 is set when 3+ CPUs
+       bfi     r1, r2, #31, #1                 // copy it to bit 31 in ACTRL
+#endif
+
+       cmp     r0, r1                          // ACTLR have SMP+<31> set?
+       bxeq    r10                             // return if set
 #endif
 
        mrc     p15, 0, r4, c1, c0, 0           // SCTLR read
@@ -547,17 +563,21 @@
 #endif
 
        // We haven't used anything from memory yet so we can invalidate the
-       // cache without fear of losing valuable data.  Note that the A5/A9
-       // L2 cache are not flushed via this call so this affects only this
-       // core's L1 cache.  The A7/A15/A17 L2 cache is write-through so
-       // invalidating it doesn't cause any data loss either.
+       // L1 cache without fear of losing valuable data.  Afterwards, we can
+       // flush icache without worrying about anything getting written back
+       // to memory.
 #if defined(KERNEL_BASES_EQUAL)
-       bl      _C_LABEL(armv7_dcache_inv_all)
+       bl      _C_LABEL(armv7_dcache_l1inv_all)// toss-dcache
+       bl      _C_LABEL(armv7_icache_inv_all)  // toss i-cache after d-cache
 #else
-       movw    ip, #:lower16:_C_LABEL(armv7_dcache_inv_all)
-       movt    ip, #:upper16:_C_LABEL(armv7_dcache_inv_all)
+       movw    ip, #:lower16:_C_LABEL(armv7_dcache_l1inv_all)
+       movt    ip, #:upper16:_C_LABEL(armv7_dcache_l1inv_all)
        sub     ip, ip, #KERNEL_BASE_VOFFSET
        blx     ip                              // toss d-cache
+       movw    ip, #:lower16:_C_LABEL(armv7_icache_inv_all)
+       movt    ip, #:upper16:_C_LABEL(armv7_icache_inv_all)
+       sub     ip, ip, #KERNEL_BASE_VOFFSET
+       blx     ip                              // toss i-cache after d-cache
 #endif
 
 #if 0