[src/trunk]: src/sys/arch/mips/mips Trailing whitespace

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/46850f1efd87
branches:  trunk
changeset: 348220:46850f1efd87
user:      skrll <skrll%NetBSD.org@localhost>
date:      Mon Oct 10 07:37:56 2016 +0000

description:
Trailing whitespace

diffstat:

 sys/arch/mips/mips/cache_r5k.c |  18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diffs (79 lines):

diff -r 175209dc6294 -r 46850f1efd87 sys/arch/mips/mips/cache_r5k.c
--- a/sys/arch/mips/mips/cache_r5k.c    Mon Oct 10 07:37:17 2016 +0000
+++ b/sys/arch/mips/mips/cache_r5k.c    Mon Oct 10 07:37:56 2016 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache_r5k.c,v 1.18 2016/10/10 07:37:17 skrll Exp $     */
+/*     $NetBSD: cache_r5k.c,v 1.19 2016/10/10 07:37:56 skrll Exp $     */
 
 /*
  * Copyright 2001 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache_r5k.c,v 1.18 2016/10/10 07:37:17 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache_r5k.c,v 1.19 2016/10/10 07:37:56 skrll Exp $");
 
 #include <sys/param.h>
 
@@ -259,7 +259,7 @@
        (void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0);
        for (; va < eva; va += 32) {
                cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
-               
+
        }
 
        mips_cp0_status_write(ostatus);
@@ -275,7 +275,7 @@
        for (; (eva - va) >= (32 * 16); va += (32 * 16)) {
                cache_r4k_op_32lines_16(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
                cache_r4k_op_32lines_16(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
-               
+
        }
 
        for (; va < eva; va += 16) {
@@ -304,7 +304,7 @@
        for (; va < eva; va += 32) {
                __asm volatile("nop; nop; nop; nop;");
                cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
-               
+
        }
 
        mips_cp0_status_write(ostatus);
@@ -328,13 +328,13 @@
        for (; (eva - va) >= (32 * 32); va += (32 * 32)) {
                (void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0);
                cache_r4k_op_32lines_32(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
-               
+
        }
 
        (void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0);
        for (; va < eva; va += 32) {
                cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
-               
+
        }
 
        mips_cp0_status_write(ostatus);
@@ -360,7 +360,7 @@
        for (; va < eva; va += 32) {
                __asm volatile("nop; nop; nop; nop;");
                cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
-               
+
        }
 
        mips_cp0_status_write(ostatus);
@@ -384,7 +384,7 @@
        for (; (eva - va) >= (32 * 32); va += (32 * 32)) {
                (void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0);
                cache_r4k_op_32lines_32(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
-               
+
        }
 
        (void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0);