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[src/trunk]: src/sys/dev/usb IQ Calibration for urtwn devices.
details: https://anonhg.NetBSD.org/src/rev/d281f6327774
branches: trunk
changeset: 348250:d281f6327774
user: nat <nat%NetBSD.org@localhost>
date: Wed Oct 12 02:56:45 2016 +0000
description:
IQ Calibration for urtwn devices.
Addresses PR/47781.
OK christos@
diffstat:
sys/dev/usb/if_urtwn.c | 151 +++++++++++++++++++++++++++++++++++++++++++++-
sys/dev/usb/if_urtwnreg.h | 45 +++++++++++++-
2 files changed, 192 insertions(+), 4 deletions(-)
diffs (263 lines):
diff -r 547108264e04 -r d281f6327774 sys/dev/usb/if_urtwn.c
--- a/sys/dev/usb/if_urtwn.c Wed Oct 12 02:50:44 2016 +0000
+++ b/sys/dev/usb/if_urtwn.c Wed Oct 12 02:56:45 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_urtwn.c,v 1.47 2016/10/12 02:50:44 nat Exp $ */
+/* $NetBSD: if_urtwn.c,v 1.48 2016/10/12 02:56:45 nat Exp $ */
/* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */
/*-
@@ -23,7 +23,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.47 2016/10/12 02:50:44 nat Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.48 2016/10/12 02:56:45 nat Exp $");
#ifdef _KERNEL_OPT
#include "opt_inet.h"
@@ -300,6 +300,14 @@
#define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p))
+static const uint16_t addaReg[] = {
+ R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA,
+ R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON,
+ R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK,
+ R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX,
+ R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN
+};
+
static int
urtwn_match(device_t parent, cfdata_t match, void *aux)
{
@@ -4104,7 +4112,144 @@
DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev),
__func__, inited));
- /* TODO */
+ uint32_t addaBackup[16], iqkBackup[4], piMode;
+
+#ifdef notyet
+ uint32_t odfm0_agccore_regs[3];
+ uint32_t ant_regs[3];
+ uint32_t rf_regs[8];
+#endif
+ uint32_t reg0, reg1, reg2;
+ int i, attempt;
+
+#ifdef notyet
+ urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc,
+ R92E_STBC_SETTING + 2));
+ urtwn_write_1(sc, R92C_ACLK_MON, 0);
+ /* Save AGCCORE regs. */
+ for (i = 0; i < sc->nrxchains; i++) {
+ odfm0_agccore_regs[i] = urtwn_read_4(sc,
+ R92C_OFDM0_AGCCORE1(i));
+ }
+#endif
+ /* Save BB regs. */
+ reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
+ reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);
+ reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));
+
+ /* Save adda regs to be restored when finished. */
+ for (i = 0; i < __arraycount(addaReg); i++)
+ addaBackup[i] = urtwn_bb_read(sc, addaReg[i]);
+ /* Save mac regs. */
+ iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE);
+ iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL);
+ iqkBackup[2] = urtwn_read_1(sc, R92C_USTIME_TSF);
+ iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG);
+
+#ifdef notyet
+ ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A);
+ ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B);
+
+ rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0));
+ for (i = 0; i < sc->nrxchains; i++)
+ rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i));
+ reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING);
+#endif
+
+ piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) &
+ R92C_HSSI_PARAM1_PI);
+ if (piMode == 0) {
+ urtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
+ urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))|
+ R92C_HSSI_PARAM1_PI);
+ urtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
+ urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))|
+ R92C_HSSI_PARAM1_PI);
+ }
+
+ attempt = 1;
+
+next_attempt:
+
+ /* Set mac regs for calibration. */
+ for (i = 0; i < __arraycount(addaReg); i++) {
+ urtwn_bb_write(sc, addaReg[i],
+ addaReg[__arraycount(addaReg) - 1]);
+ }
+ urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc,
+ R92C_CCK0_AFESETTING));
+ urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA);
+ urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR);
+ urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1);
+ urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM);
+
+ if (sc->ntxchains > 1)
+ urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM);
+
+ urtwn_write_1(sc, R92C_TXPAUSE, (~TP_STOPBECON) & TP_STOPALL);
+ urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] &
+ ~R92C_BCN_CTRL_EN_BCN));
+ urtwn_write_1(sc, R92C_USTIME_TSF, (iqkBackup[2] & ~0x8));
+
+ urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] &
+ ~R92C_GPIO_MUXCFG_ENBT));
+
+ urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT);
+
+ if (sc->ntxchains > 1)
+ urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT);
+ urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING);
+ urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING);
+ urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING);
+
+ /* Restore BB regs. */
+ urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0);
+ urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2);
+ urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1);
+
+ urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0);
+ urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE);
+ if (sc->nrxchains > 1)
+ urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE);
+
+ if (attempt-- > 0)
+ goto next_attempt;
+
+ /* Restore mode. */
+ if (piMode == 0) {
+ urtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
+ urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) &
+ ~R92C_HSSI_PARAM1_PI);
+ urtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
+ urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) &
+ ~R92C_HSSI_PARAM1_PI);
+ }
+
+#ifdef notyet
+ for (i = 0; i < sc->nrxchains; i++) {
+ urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i),
+ odfm0_agccore_regs[i]);
+ }
+#endif
+
+ /* Restore adda regs. */
+ for (i = 0; i < __arraycount(addaReg); i++)
+ urtwn_bb_write(sc, addaReg[i], addaBackup[i]);
+ /* Restore mac regs. */
+ urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]);
+ urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]);
+ urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]);
+ urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]);
+
+#ifdef notyet
+ urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]);
+ urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]);
+
+ urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]);
+ for (i = 0; i < sc->nrxchains; i++)
+ urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]);
+ urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4);
+#endif
}
static void
diff -r 547108264e04 -r d281f6327774 sys/dev/usb/if_urtwnreg.h
--- a/sys/dev/usb/if_urtwnreg.h Wed Oct 12 02:50:44 2016 +0000
+++ b/sys/dev/usb/if_urtwnreg.h Wed Oct 12 02:56:45 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_urtwnreg.h,v 1.8 2016/04/23 10:15:32 skrll Exp $ */
+/* $NetBSD: if_urtwnreg.h,v 1.9 2016/10/12 02:56:45 nat Exp $ */
/* $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ */
/*-
@@ -437,6 +437,16 @@
#define R92C_PBP_512 3
#define R92C_PBP_1024 4
+/* Bits for R92C_TXPAUSE. */
+#define TP_STOPBECON 0x40
+#define TP_STOPHIGH 0x20
+#define TP_STOPMGT 0x10
+#define TP_STOPVO 0x08
+#define TP_STOPVI 0x04
+#define TP_STOPBE 0x02
+#define TP_STOPBK 0x01
+#define TP_STOPALL 0x6f
+
/* Bits for R92C_TRXDMA_CTRL. */
#define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004
#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030
@@ -584,6 +594,7 @@
#define R92C_TXAGC_A_CCK1_MCS32 0xe08
#define R92C_FPGA0_XA_HSSIPARAM1 0x820
#define R92C_TXAGC_B_CCK1_55_MCS32 0x838
+#define R92C_FPGA0_XCD_SWITCHCTL 0x85c
#define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c
#define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c)
#define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848)
@@ -600,6 +611,8 @@
#define R92C_FPGA1_TXINFO 0x90c
#define R92C_CCK0_SYSTEM 0xa00
#define R92C_CCK0_AFESETTING 0xa04
+#define R92C_CONFIG_ANT_A 0xb68
+#define R92C_CONFIG_ANT_B 0xb6c
#define R92C_OFDM0_TRXPATHENA 0xc04
#define R92C_OFDM0_TRMUXPAR 0xc08
#define R92C_OFDM0_XARXIQIMBALANCE 0xc14
@@ -615,6 +628,25 @@
#define R92C_OFDM0_XDTXAFE 0xc9c
#define R92C_OFDM0_RXIQEXTANTA 0xca0
#define R92C_OFDM1_LSTF 0xd00
+#define R92C_FPGA0_IQK 0xe28
+#define R92C_TX_IQK 0xe40
+#define R92C_RX_IQK 0xe44
+#define R92C_BLUETOOTH 0xe6c
+#define R92C_RX_WAIT_CCA 0xe70
+#define R92C_TX_CCK_RFON 0xe74
+#define R92C_TX_CCK_BBON 0xe78
+#define R92C_TX_OFDM_RFON 0xe7c
+#define R92C_TX_OFDM_BBON 0xe80
+#define R92C_TX_TO_RX 0xe84
+#define R92C_TX_TO_TX 0xe88
+#define R92C_RX_CCK 0xe8c
+#define R92C_RX_OFDM 0xed0
+#define R92C_RX_WAIT_RIFS 0xed4
+#define R92C_RX_TO_RX 0xed8
+#define R92C_STANDBY 0xedc
+#define R92C_SLEEP 0xee0
+#define R92C_PMPD_ANAEN 0xeec
+
/* Bits for R92C_FPGA[01]_RFMOD. */
#define R92C_RFMOD_40MHZ 0x00000001
@@ -1112,3 +1144,14 @@
uint16_t txdsum;
uint16_t pad;
} __packed __aligned(4);
+
+/* Values for IQ calibration. */
+#define R92C_IQK_TRXPATHENA 0x5600
+#define R92C_IQK_TRMUXPAR 0x00e4
+#define R92C_IQK_RFIFACESW1 0x8200
+#define R92C_IQK_LSSI_PARAM 0x00010000
+#define R92C_IQK_LSSI_RESTORE 0x00032ed3
+#define R92C_IQK_CONFIG_ANT 0x00080000
+#define R92C_TX_IQK_SETTING 0x01007c00
+#define R92C_RX_IQK_SETTING 0x01004800
+#define R92C_FPGA0_IQK_SETTING 0x80800000
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