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[src/trunk]: src/sys/arch/arm fix Marvell Coherency Barrier register address.
details: https://anonhg.NetBSD.org/src/rev/99a086b6722a
branches: trunk
changeset: 338347:99a086b6722a
user: hsuenaga <hsuenaga%NetBSD.org@localhost>
date: Tue May 19 09:20:19 2015 +0000
description:
fix Marvell Coherency Barrier register address.
configure coherency bus maintance broadcast using MPIDR. we need to configure
this regardless of 'options MULTIPROCESSOR.'
diffstat:
sys/arch/arm/arm/cpufunc_asm_pj4b.S | 39 +++++++++++++++++++++++++-----------
sys/arch/arm/marvell/armadaxp.c | 14 ++++++------
sys/arch/arm/marvell/mvsocreg.h | 29 +++++++++++++++++++-------
3 files changed, 55 insertions(+), 27 deletions(-)
diffs (186 lines):
diff -r a9b1ec8d039d -r 99a086b6722a sys/arch/arm/arm/cpufunc_asm_pj4b.S
--- a/sys/arch/arm/arm/cpufunc_asm_pj4b.S Tue May 19 08:14:38 2015 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_pj4b.S Tue May 19 09:20:19 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_pj4b.S,v 1.9 2015/05/14 17:15:56 matt Exp $ */
+/* $NetBSD: cpufunc_asm_pj4b.S,v 1.10 2015/05/19 09:20:19 hsuenaga Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -41,6 +41,16 @@
#include <arm/asm.h>
#include <arm/locore.h>
+#define MV_FMC0_SMP (1 << 1) /* SMP/nAMP enable */
+#define MV_FMC0_PARITY (1 << 2) /* Enable L1 Cache Parity */
+#define MV_FMC0_LFDIS (1 << 7) /* Disable DC Speculative linefill*/
+#define MV_FMC0_FW (1 << 8) /* Cache & TLB maintenance broadcast */
+
+#define MPIDR_CPUID_MASK (0x3 << 0) /* CPUID */
+#define MPIDR_CLUSTERID_MASK (0xf << 8) /* CLUSTERID */
+#define MPIDR_UNI_PROCESSOR (1 << 30) /* Uni-Processor System */
+#define MPIDR_MPCORE (1 << 31) /* New Style MPCore like CortexA9 */
+
/* LINTSTUB: void pj4b_cpu_sleep(int); */
ENTRY(pj4b_cpu_sleep)
dsb
@@ -51,21 +61,21 @@
/* LINTSTUB: void pj4b_config(void); */
ENTRY(pj4b_config)
- /* Set Auxiliary Debug Modes Control 0 register */
+ /* Set Marvell Auxiliary Debug Modes Control 0 register */
mrc p15, 1, r0, c15, c1, 0
bic r0, r0, #(1 << 12) @ Erratum#ARM-CPU-6136
@ LDSTM 1st issue is single word
orr r0, r0, #(1 << 22) @ DVM_WAKEUP enable
mcr p15, 1, r0, c15, c1, 0
- /* Set Auxiliary Debug Modes Control 1 register */
+ /* Set Marvell Auxiliary Debug Modes Control 1 register */
mrc p15, 1, r0, c15, c1, 1
bic r0, r0, #(1 << 2) @ Erratum#ARM-CPU-6409
@ Disable static branch prediction
orr r0, r0, #(1 << 5) @ STREX backoff disable
mcr p15, 1, r0, c15, c1, 1
- /* Set Auxiliary Debug Modes Control 2 register */
+ /* Set Marvell Auxiliary Debug Modes Control 2 register */
mrc p15, 1, r0, c15, c1, 2
bic r0, r0, #(1 << 23) @ Enable fast LDR
orr r0, r0, #(1 << 25) @ Intervention Interleave disable
@@ -75,13 +85,18 @@
orr r0, r0, #(1 << 31) @ Enable write evict
mcr p15, 1, r0, c15, c1, 2
- /* Set Auxiliary FUnction Modes Control 0 register */
- mrc p15, 1, r0, c15, c2, 0
-#ifdef MULTIPROCESSOR
- orr r0, r0, #(1 << 1) @ SMP/nAMP enable
-#endif
- orr r0, r0, #(1 << 2) @ L2 parity enable
- orr r0, r0, #(1 << 8) @ Cache & TLB maintenance broadcast
+ /* Set Marvell Auxiliary Function Modes Control 0 register */
+ mrc p15, 1, r0, c15, c2, 0 @ get FMC0
+ mrc p15, 0, ip, c0, c0, 5 @ get MPIDR
+ tst ip, #MPIDR_MPCORE
+ beq 1f @ if not set, not a MPCORE
+ tst ip, #MPIDR_UNI_PROCESSOR
+ bne 1f @ if set, uni-processor system
+ orr r0, r0, #(MV_FMC0_SMP) @ enable SMP/nAMP
+ orr r0, r0, #(MV_FMC0_FW) @ enable maintenance bcast
+1:
+ bic r0, r0, #(MV_FMC0_LFDIS) @ enable speculative linefill
+ orr r0, r0, #(MV_FMC0_PARITY) @ enable L1 parity
mcr p15, 1, r0, c15, c2, 0
RET
@@ -97,7 +112,7 @@
1:
ldr r1, [r0]
tst r1, #1
- beq 1b
+ bne 1b @ if set, CIB is busy.
dsb
RET
END(pj4b_io_coherency_barrier)
diff -r a9b1ec8d039d -r 99a086b6722a sys/arch/arm/marvell/armadaxp.c
--- a/sys/arch/arm/marvell/armadaxp.c Tue May 19 08:14:38 2015 +0000
+++ b/sys/arch/arm/marvell/armadaxp.c Tue May 19 09:20:19 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxp.c,v 1.13 2015/05/14 05:39:32 hsuenaga Exp $ */
+/* $NetBSD: armadaxp.c,v 1.14 2015/05/19 09:20:19 hsuenaga Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -37,7 +37,7 @@
*******************************************************************************/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.13 2015/05/14 05:39:32 hsuenaga Exp $");
+__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.14 2015/05/19 09:20:19 hsuenaga Exp $");
#define _INTR_PRIVATE
@@ -49,7 +49,6 @@
#include <machine/intr.h>
#include <arm/pic/picvar.h>
-#include <arm/pic/picvar.h>
#include <arm/armreg.h>
#include <arm/cpu.h>
@@ -434,7 +433,8 @@
}
/* Variables for cpufunc_asm_pj4b.S */
- armadaxp_l2_barrier_reg = mlmb_base + MVSOC_MLMB_CIB_BARRIER_TRIGGER;
+ /* XXX: per cpu register. need to support SMP */
+ armadaxp_l2_barrier_reg = mlmb_base + MVSOC_MLMB_CIB_BARRIER(0);
/* Set L2 policy */
reg = L2_READ(ARMADAXP_L2_AUX_CTRL);
@@ -624,9 +624,9 @@
write_mlmbreg(MVSOC_MLMB_CIB_CTRL_CFG, reg);
/* enable CPUs in SMP group on Fabric coherency */
- reg = read_mlmbreg(MVSOC_MLMB_CFU_CTRL);
- reg |= MVSOC_MLMB_CFU_CTRL_SNOOP_CPU0;
- write_mlmbreg(MVSOC_MLMB_CFU_CTRL, reg);
+ reg = read_mlmbreg(MVSOC_MLMB_CFU_FAB_CTRL);
+ reg |= MVSOC_MLMB_CFU_FAB_CTRL_SNOOP_CPU0;
+ write_mlmbreg(MVSOC_MLMB_CFU_FAB_CTRL, reg);
/* send all snoop request to L2 cache */
reg = read_mlmbreg(MVSOC_MLMB_CFU_CFG);
diff -r a9b1ec8d039d -r 99a086b6722a sys/arch/arm/marvell/mvsocreg.h
--- a/sys/arch/arm/marvell/mvsocreg.h Tue May 19 08:14:38 2015 +0000
+++ b/sys/arch/arm/marvell/mvsocreg.h Tue May 19 09:20:19 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsocreg.h,v 1.10 2015/05/14 05:39:32 hsuenaga Exp $ */
+/* $NetBSD: mvsocreg.h,v 1.11 2015/05/19 09:20:19 hsuenaga Exp $ */
/*
* Copyright (c) 2007, 2008 KIYOHARA Takashi
* All rights reserved.
@@ -128,13 +128,26 @@
#define MVSOC_MLMB_WINCR_WINCS(x) (((x) & 0x1c) >> 2)
#define MVSOC_MLMB_WINCR_SIZE_MASK 0xff000000
-/* Coherent Fabric Control and Status */
-#define MVSOC_MLMB_CFU_CTRL 0x200
-#define MVSOC_MLMB_CFU_CTRL_PROP_ERR (0x1 << 8)
-#define MVSOC_MLMB_CFU_CTRL_SNOOP_CPU0 (0x1 << 24)
+/* Coherent Fabric(CFU) Control and Status */
+#define MVSOC_MLMB_CFU_FAB_CTRL 0x200
+#define MVSOC_MLMB_CFU_FAB_CTRL_PROP_ERR (0x1 << 8)
+#define MVSOC_MLMB_CFU_FAB_CTRL_SNOOP_CPU0 (0x1 << 24)
+#define MVSOC_MLMB_CFU_FAB_CTRL_SNOOP_CPU1 (0x1 << 25)
+#define MVSOC_MLMB_CFU_FAB_CTRL_SNOOP_CPU2 (0x1 << 26)
+#define MVSOC_MLMB_CFU_FAB_CTRL_SNOOP_CPU3 (0x1 << 27)
-#define MVSOC_MLMB_CFU_CFG 0x228
-#define MVSOC_MLMB_CFU_CFG_L2_NOTIFY (0x1 << 16)
+/* Coherent Fabiric Configuration */
+#define MVSOC_MLMB_CFU_FAB_CFG 0x204
+
+/* CFU IO Event Affinity */
+#define MVSOC_MLMB_CFU_EVA 0x208
+
+/* CFU IO Snoop Affinity */
+#define MVSOC_MLMB_CFU_IOA 0x20c
+
+/* CFU Configuration XXX: changed in ARMADA 370 */
+#define MVSOC_MLMB_CFU_CFG 0x228
+#define MVSOC_MLMB_CFU_CFG_L2_NOTIFY (0x1 << 16)
/* CIB registers offsets */
#define MVSOC_MLMB_CIB_CTRL_CFG 0x280
@@ -144,7 +157,7 @@
#define MVSOC_MLMB_CIB_CTRL_CFG_EMPTY (0x1 << 13)
/* CIB barrier register */
-#define MVSOC_MLMB_CIB_BARRIER 0x1810
+#define MVSOC_MLMB_CIB_BARRIER(cpu) (0x1810 + 0x100 * (cpu))
#define MVSOC_MLMB_CIB_BARRIER_TRIGGER (0x1 << 0)
#define MVSOC_TMR_BASE (MVSOC_MLMB_BASE + 0x0300)
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