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[src/trunk]: src/sys add support iMX6 uSDHC
details: https://anonhg.NetBSD.org/src/rev/eb8487383121
branches: trunk
changeset: 342606:eb8487383121
user: ryo <ryo%NetBSD.org@localhost>
date: Thu Dec 31 11:53:18 2015 +0000
description:
add support iMX6 uSDHC
- some UHS-I/SDR104 card are not stable
- eMMC doesn't work yet
diffstat:
sys/arch/arm/imx/imx6_iomuxreg.h | 2255 ++++++++++++++++++------
sys/arch/arm/imx/imx6_usdhc.c | 106 +-
sys/arch/evbarm/conf/CUBOX-I | 8 +-
sys/arch/evbarm/conf/NITROGEN6X | 12 +-
sys/arch/evbarm/nitrogen6/nitrogen6_iomux.c | 504 +++++-
sys/arch/evbarm/nitrogen6/nitrogen6_machdep.c | 7 +-
sys/dev/sdmmc/sdhc.c | 154 +-
sys/dev/sdmmc/sdhcreg.h | 31 +-
sys/dev/sdmmc/sdhcvar.h | 3 +-
9 files changed, 2418 insertions(+), 662 deletions(-)
diffs (truncated from 3541 to 300 lines):
diff -r 56dd92df1fa1 -r eb8487383121 sys/arch/arm/imx/imx6_iomuxreg.h
--- a/sys/arch/arm/imx/imx6_iomuxreg.h Thu Dec 31 10:56:13 2015 +0000
+++ b/sys/arch/arm/imx/imx6_iomuxreg.h Thu Dec 31 11:53:18 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx6_iomuxreg.h,v 1.2 2015/07/30 08:09:36 ryo Exp $ */
+/* $NetBSD: imx6_iomuxreg.h,v 1.3 2015/12/31 11:53:18 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -104,581 +104,1678 @@
#define IOMUX_GPR13_SATA_PHY_2(n) __SHIFTIN(n, __BITS(6, 2))
#define IOMUX_GPR13_SATA_PHY_1(n) __SHIFTIN(n, __BIT(1))
#define IOMUX_GPR13_SATA_PHY_0(n) __SHIFTIN(n, __BIT(0))
-#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 0x0000004c
-#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 0x00000050
-#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 0x00000054
-#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC 0x00000058
-#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0 0x0000005c
-#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1 0x00000060
-#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2 0x00000064
-#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3 0x00000068
-#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL 0x0000006c
-#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0 0x00000070
-#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL 0x00000074
-#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1 0x00000078
-#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2 0x0000007c
-#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3 0x00000080
-#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC 0x00000084
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25 0x00000088
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_B 0x0000008c
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16 0x00000090
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17 0x00000094
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18 0x00000098
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19 0x0000009c
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x000000a0
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x000000a4
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22 0x000000a8
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23 0x000000ac
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_B 0x000000b0
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24 0x000000b4
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25 0x000000b8
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26 0x000000bc
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27 0x000000c0
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x000000c4
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29 0x000000c8
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30 0x000000cc
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31 0x000000d0
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24 0x000000d4
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23 0x000000d8
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22 0x000000dc
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21 0x000000e0
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20 0x000000e4
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19 0x000000e8
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18 0x000000ec
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17 0x000000f0
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16 0x000000f4
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B 0x000000f8
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_B 0x000000fc
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B 0x00000100
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_RW 0x00000104
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B 0x00000108
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_B 0x0000010c
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_B 0x00000110
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD00 0x00000114
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD01 0x00000118
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD02 0x0000011c
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD03 0x00000120
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD04 0x00000124
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD05 0x00000128
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD06 0x0000012c
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD07 0x00000130
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD08 0x00000134
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD09 0x00000138
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD10 0x0000013c
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD11 0x00000140
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD12 0x00000144
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD13 0x00000148
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD14 0x0000014c
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 0x00000150
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B 0x00000154
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK 0x00000158
-#define IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK 0x0000015c
-#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15 0x00000160
-#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02 0x00000164
-#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03 0x00000168
-#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04 0x0000016c
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00 0x00000170
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01 0x00000174
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02 0x00000178
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03 0x0000017c
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04 0x00000180
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05 0x00000184
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06 0x00000188
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07 0x0000018c
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08 0x00000190
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09 0x00000194
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10 0x00000198
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11 0x0000019c
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12 0x000001a0
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13 0x000001a4
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14 0x000001a8
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15 0x000001ac
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16 0x000001b0
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17 0x000001b4
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18 0x000001b8
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19 0x000001bc
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20 0x000001c0
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21 0x000001c4
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22 0x000001c8
-#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23 0x000001cc
-#define IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO 0x000001d0
-#define IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK 0x000001d4
-#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER 0x000001d8
-#define IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV 0x000001dc
-#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1 0x000001e0
-#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0 0x000001e4
-#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN 0x000001e8
-#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1 0x000001ec
-#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0 0x000001f0
-#define IOMUXC_SW_MUX_CTL_PAD_ENET_MDC 0x000001f4
-#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x000001f8
-#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x000001fc
-#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x00000200
-#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x00000204
-#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x00000208
-#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x0000020c
-#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x00000210
-#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x00000214
-#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 0x00000218
-#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 0x0000021c
-#define IOMUXC_SW_MUX_CTL_PAD_GPIO00 0x00000220
-#define IOMUXC_SW_MUX_CTL_PAD_GPIO01 0x00000224
-#define IOMUXC_SW_MUX_CTL_PAD_GPIO09 0x00000228
-#define IOMUXC_SW_MUX_CTL_PAD_GPIO03 0x0000022c
-#define IOMUXC_SW_MUX_CTL_PAD_GPIO06 0x00000230
-#define IOMUXC_SW_MUX_CTL_PAD_GPIO02 0x00000234
-#define IOMUXC_SW_MUX_CTL_PAD_GPIO04 0x00000238
-#define IOMUXC_SW_MUX_CTL_PAD_GPIO05 0x0000023c
-#define IOMUXC_SW_MUX_CTL_PAD_GPIO07 0x00000240
-#define IOMUXC_SW_MUX_CTL_PAD_GPIO08 0x00000244
-#define IOMUXC_SW_MUX_CTL_PAD_GPIO16 0x00000248
-#define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x0000024c
-#define IOMUXC_SW_MUX_CTL_PAD_GPIO18 0x00000250
-#define IOMUXC_SW_MUX_CTL_PAD_GPIO19 0x00000254
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK 0x00000258
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC 0x0000025c
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN 0x00000260
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC 0x00000264
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04 0x00000268
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05 0x0000026c
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06 0x00000270
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07 0x00000274
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08 0x00000278
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09 0x0000027c
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10 0x00000280
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11 0x00000284
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12 0x00000288
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13 0x0000028c
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14 0x00000290
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15 0x00000294
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16 0x00000298
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17 0x0000029c
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18 0x000002a0
-#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19 0x000002a4
-#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x000002a8
-#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x000002ac
-#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5 0x000002b0
-#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4 0x000002b4
-#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD 0x000002b8
-#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK 0x000002bc
-#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x000002c0
-#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x000002c4
-#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 0x000002c8
-#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3 0x000002cc
-#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET 0x000002d0
-#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x000002d4
-#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x000002d8
-#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x000002dc
-#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B 0x000002e0
-#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B 0x000002e4
-#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B 0x000002e8
-#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B 0x000002ec
-#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B 0x000002f0
-#define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x000002f4
-#define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x000002f8
-#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x000002fc
-#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x00000300
-#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x00000304
-#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x00000308
-#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x0000030c
-#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x00000310
-#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x00000314
-#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x00000318
-#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0 0x0000031c
-#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1 0x00000320
-#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2 0x00000324
-#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3 0x00000328
-#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4 0x0000032c
-#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5 0x00000330
-#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6 0x00000334
-#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7 0x00000338
-#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 0x0000033c
-#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 0x00000340
-#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 0x00000344
-#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD 0x00000348
-#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 0x0000034c
-#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK 0x00000350
-#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK 0x00000354
-#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD 0x00000358
-#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 0x0000035c
-#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 0x00000360
-#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 0x00000364
-#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 0x00000368
-#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC 0x0000036c
-#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0 0x00000370
-#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1 0x00000374
-#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2 0x00000378
-#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3 0x0000037c
-#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL 0x00000380
-#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0 0x00000384
-#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL 0x00000388
-#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1 0x0000038c
-#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2 0x00000390
-#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3 0x00000394
-#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC 0x00000398
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25 0x0000039c
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_B 0x000003a0
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16 0x000003a4
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17 0x000003a8
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18 0x000003ac
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19 0x000003b0
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 0x000003b4
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x000003b8
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22 0x000003bc
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23 0x000003c0
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_B 0x000003c4
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24 0x000003c8
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25 0x000003cc
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26 0x000003d0
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27 0x000003d4
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x000003d8
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29 0x000003dc
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30 0x000003e0
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31 0x000003e4
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24 0x000003e8
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23 0x000003ec
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22 0x000003f0
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21 0x000003f4
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20 0x000003f8
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19 0x000003fc
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18 0x00000400
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17 0x00000404
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16 0x00000408
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B 0x0000040c
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_B 0x00000410
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B 0x00000414
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_RW 0x00000418
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B 0x0000041c
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_B 0x00000420
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_B 0x00000424
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD00 0x00000428
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD01 0x0000042c
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD02 0x00000430
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD03 0x00000434
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD04 0x00000438
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD05 0x0000043c
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD06 0x00000440
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD07 0x00000444
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD08 0x00000448
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD09 0x0000044c
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD10 0x00000450
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD11 0x00000454
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD12 0x00000458
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD13 0x0000045c
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD14 0x00000460
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD15 0x00000464
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B 0x00000468
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK 0x0000046c
-#define IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK 0x00000470
-#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15 0x00000474
-#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02 0x00000478
-#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03 0x0000047c
-#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04 0x00000480
-#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00 0x00000484
-#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01 0x00000488
-#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02 0x0000048c
-#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03 0x00000490
-#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04 0x00000494
-#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05 0x00000498
-#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06 0x0000049c
-#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07 0x000004a0
-#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08 0x000004a4
-#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09 0x000004a8
-#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10 0x000004ac
-#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11 0x000004b0
-#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12 0x000004b4
-#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13 0x000004b8
-#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14 0x000004bc
-#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15 0x000004c0
-#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16 0x000004c4
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