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[src/trunk]: src/sys/arch Initial import of Cavium Octeon and Octeon Plus SoC...
details: https://anonhg.NetBSD.org/src/rev/1e9fc7ffbbca
branches: trunk
changeset: 337820:1e9fc7ffbbca
user: hikaru <hikaru%NetBSD.org@localhost>
date: Wed Apr 29 08:32:00 2015 +0000
description:
Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.
diffstat:
sys/arch/evbmips/cavium/autoconf.c | 184 +
sys/arch/evbmips/cavium/mach_intr.c | 67 +
sys/arch/evbmips/cavium/machdep.c | 434 ++
sys/arch/evbmips/cavium/octeon_bootbus_machdep.c | 42 +
sys/arch/evbmips/cavium/octeon_uboot.h | 58 +
sys/arch/evbmips/conf/ERLITE | 175 +
sys/arch/evbmips/conf/files.octeon | 13 +
sys/arch/mips/cavium/autoconf.h | 46 +
sys/arch/mips/cavium/dev/if_cnmac.c | 1908 +++++++++
sys/arch/mips/cavium/dev/if_cnmacvar.h | 161 +
sys/arch/mips/cavium/dev/octeon_asx.c | 249 +
sys/arch/mips/cavium/dev/octeon_asxreg.h | 268 +
sys/arch/mips/cavium/dev/octeon_asxvar.h | 56 +
sys/arch/mips/cavium/dev/octeon_bootbusreg.h | 247 +
sys/arch/mips/cavium/dev/octeon_ciu.c | 131 +
sys/arch/mips/cavium/dev/octeon_ciureg.h | 668 +++
sys/arch/mips/cavium/dev/octeon_cop2reg.h | 128 +
sys/arch/mips/cavium/dev/octeon_cop2var.h | 1038 ++++
sys/arch/mips/cavium/dev/octeon_corereg.h | 627 ++
sys/arch/mips/cavium/dev/octeon_fau.c | 164 +
sys/arch/mips/cavium/dev/octeon_faureg.h | 41 +
sys/arch/mips/cavium/dev/octeon_fauvar.h | 138 +
sys/arch/mips/cavium/dev/octeon_fpa.c | 521 ++
sys/arch/mips/cavium/dev/octeon_fpareg.h | 375 +
sys/arch/mips/cavium/dev/octeon_fpavar.h | 157 +
sys/arch/mips/cavium/dev/octeon_gmx.c | 1637 +++++++
sys/arch/mips/cavium/dev/octeon_gmxreg.h | 1170 +++++
sys/arch/mips/cavium/dev/octeon_gmxvar.h | 175 +
sys/arch/mips/cavium/dev/octeon_gpioreg.h | 126 +
sys/arch/mips/cavium/dev/octeon_iobreg.h | 57 +
sys/arch/mips/cavium/dev/octeon_ipd.c | 458 ++
sys/arch/mips/cavium/dev/octeon_ipdreg.h | 732 +++
sys/arch/mips/cavium/dev/octeon_ipdvar.h | 73 +
sys/arch/mips/cavium/dev/octeon_l2creg.h | 69 +
sys/arch/mips/cavium/dev/octeon_mpi.c | 255 +
sys/arch/mips/cavium/dev/octeon_mpireg.h | 135 +
sys/arch/mips/cavium/dev/octeon_mpivar.h | 19 +
sys/arch/mips/cavium/dev/octeon_npireg.h | 434 ++
sys/arch/mips/cavium/dev/octeon_pci.c | 113 +
sys/arch/mips/cavium/dev/octeon_pcmreg.h | 112 +
sys/arch/mips/cavium/dev/octeon_pip.c | 397 +
sys/arch/mips/cavium/dev/octeon_pipreg.h | 975 ++++
sys/arch/mips/cavium/dev/octeon_pipvar.h | 81 +
sys/arch/mips/cavium/dev/octeon_pko.c | 253 +
sys/arch/mips/cavium/dev/octeon_pkoreg.h | 396 +
sys/arch/mips/cavium/dev/octeon_pkovar.h | 165 +
sys/arch/mips/cavium/dev/octeon_pow.c | 1127 +++++
sys/arch/mips/cavium/dev/octeon_powreg.h | 1005 ++++
sys/arch/mips/cavium/dev/octeon_powvar.h | 504 ++
sys/arch/mips/cavium/dev/octeon_rnm.c | 197 +
sys/arch/mips/cavium/dev/octeon_rnmreg.h | 88 +
sys/arch/mips/cavium/dev/octeon_smi.c | 139 +
sys/arch/mips/cavium/dev/octeon_smireg.h | 88 +
sys/arch/mips/cavium/dev/octeon_smivar.h | 51 +
sys/arch/mips/cavium/dev/octeon_tim.c | 178 +
sys/arch/mips/cavium/dev/octeon_timreg.h | 192 +
sys/arch/mips/cavium/dev/octeon_twsi.c | 537 ++
sys/arch/mips/cavium/dev/octeon_twsireg.h | 181 +
sys/arch/mips/cavium/dev/octeon_uart.c | 211 +
sys/arch/mips/cavium/dev/octeon_uartreg.h | 124 +
sys/arch/mips/cavium/dev/octeon_usbc.c | 4627 ++++++++++++++++++++++
sys/arch/mips/cavium/dev/octeon_usbcreg.h | 1077 +++++
sys/arch/mips/cavium/dev/octeon_usbcvar.h | 324 +
sys/arch/mips/cavium/dev/octeon_usbn.c | 438 ++
sys/arch/mips/cavium/dev/octeon_usbnreg.h | 376 +
sys/arch/mips/cavium/dev/octeon_usbnvar.h | 40 +
sys/arch/mips/cavium/include/bootbusvar.h | 65 +
sys/arch/mips/cavium/include/iobusvar.h | 65 +
sys/arch/mips/cavium/include/mainbusvar.h | 40 +
sys/arch/mips/cavium/mainbus.c | 96 +
sys/arch/mips/cavium/mainbus_octeon1p.c | 51 +
sys/arch/mips/cavium/octeon1p_iobus.c | 146 +
sys/arch/mips/cavium/octeon_bootbus.c | 148 +
sys/arch/mips/cavium/octeon_dma.c | 74 +
sys/arch/mips/cavium/octeon_intr.c | 435 ++
sys/arch/mips/cavium/octeon_iobus.c | 214 +
sys/arch/mips/cavium/octeonvar.h | 407 +
sys/arch/mips/conf/files.mips | 4 +-
sys/arch/mips/conf/files.octeon | 92 +
sys/arch/mips/conf/std.octeon | 25 +
sys/arch/mips/include/cache_octeon.h | 56 +
sys/arch/mips/include/cpuregs.h | 20 +-
sys/arch/mips/include/locore.h | 36 +-
sys/arch/mips/mips/cache.c | 42 +-
sys/arch/mips/mips/cache_octeon.c | 286 +
sys/arch/mips/mips/locore_octeon.S | 117 +
sys/arch/mips/mips/mips_machdep.c | 66 +-
87 files changed, 29700 insertions(+), 17 deletions(-)
diffs (truncated from 30186 to 300 lines):
diff -r 1363f328ad9a -r 1e9fc7ffbbca sys/arch/evbmips/cavium/autoconf.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/evbmips/cavium/autoconf.c Wed Apr 29 08:32:00 2015 +0000
@@ -0,0 +1,184 @@
+/* $NetBSD: autoconf.c,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+
+/*
+ * Copyright 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Simon Burge for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.1 2015/04/29 08:32:01 hikaru Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/buf.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+
+#include <net/if_ether.h>
+
+#include <machine/cpu.h>
+
+#include <evbmips/cavium/octeon_uboot.h>
+
+static void findroot(void);
+
+void
+cpu_configure(void)
+{
+
+ intr_init();
+
+ /* Kick off autoconfiguration. */
+ (void)splhigh();
+ if (config_rootfound("mainbus", NULL) == NULL)
+ panic("no mainbus found");
+
+ /* XXX need this? */
+ (void)spl0();
+}
+
+void
+cpu_rootconf(void)
+{
+ findroot();
+
+ printf("boot device: %s\n",
+ booted_device ? booted_device->dv_xname : "<unknown>");
+
+ rootconf();
+}
+
+extern char bootstring[];
+extern int netboot;
+
+static void
+findroot(void)
+{
+ device_t dv;
+ deviter_t di;
+
+ if (booted_device)
+ return;
+
+ if ((booted_device == NULL) && netboot == 0) {
+ for (dv = deviter_first(&di, DEVITER_F_ROOT_FIRST); dv != NULL;
+ dv = deviter_next(&di)) {
+ if (device_class(dv) == DV_DISK &&
+ device_is_a(dv, "wd"))
+ booted_device = dv;
+ }
+ deviter_release(&di);
+ }
+
+ /*
+ * XXX Match up MBR boot specification with BSD disklabel for root?
+ */
+ booted_partition = 0;
+
+ return;
+}
+
+static void
+prop_set_cnmac(device_t dev)
+{
+ prop_dictionary_t dict = device_properties(dev);
+ prop_data_t pd;
+ prop_number_t pn;
+ uint8_t enaddr[ETHER_ADDR_LEN];
+ uint32_t mac_lo;
+ int unit = device_unit(dev);
+
+ /* ethernet mac address */
+ memcpy(enaddr, octeon_btinfo.obt_mac_addr_base,
+ sizeof(enaddr));
+ mac_lo = enaddr[3] << 16;
+ mac_lo += enaddr[4] << 8;
+ mac_lo += enaddr[5];
+ KASSERT(unit < octeon_btinfo.obt_mac_addr_count);
+ mac_lo += unit;
+ enaddr[3] = (mac_lo >> 16) & 0xff;
+ enaddr[4] = (mac_lo >> 8) & 0xff;
+ enaddr[5] = mac_lo & 0xff;
+ pd = prop_data_create_data(enaddr, ETHER_ADDR_LEN);
+ KASSERT(pd != NULL);
+ prop_dictionary_set_and_rel(dict, "mac-address", pd);
+
+ /* ethernet phy adddress */
+ switch (octeon_btinfo.obt_board_type) {
+ case BOARD_TYPE_UBIQUITI_E100:
+ pn = prop_number_create_integer(0x07 - unit);
+ break;
+ default:
+ pn = prop_number_create_integer(-1);
+ break;
+ }
+ KASSERT(pn != NULL);
+ prop_dictionary_set_and_rel(dict, "phy-addr", pn);
+}
+
+static void
+prop_set_octeon_gmx(device_t dev)
+{
+ prop_dictionary_t dict = device_properties(dev);
+ prop_number_t tx, rx;
+
+ /* ethernet rgmii phy dependent timing parameter. */
+ switch (octeon_btinfo.obt_board_type) {
+ case BOARD_TYPE_UBIQUITI_E100:
+ tx = prop_number_create_integer(16);
+ rx = prop_number_create_integer(0);
+ break;
+ default:
+ tx = prop_number_create_integer(0);
+ rx = prop_number_create_integer(0);
+ break;
+ }
+ KASSERT(tx != NULL);
+ KASSERT(rx != NULL);
+ prop_dictionary_set_and_rel(dict, "rgmii-tx", tx);
+ prop_dictionary_set_and_rel(dict, "rgmii-rx", rx);
+}
+
+void
+device_register(device_t dev, void *aux)
+{
+ if ((booted_device == NULL) && (netboot == 1))
+ if (device_class(dev) == DV_IFNET)
+ booted_device = dev;
+
+ if (device_is_a(dev, "cnmac")) {
+ prop_set_cnmac(dev);
+ } else if (device_is_a(dev, "octeon_gmx")) {
+ prop_set_octeon_gmx(dev);
+ }
+}
diff -r 1363f328ad9a -r 1e9fc7ffbbca sys/arch/evbmips/cavium/mach_intr.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/evbmips/cavium/mach_intr.c Wed Apr 29 08:32:00 2015 +0000
@@ -0,0 +1,67 @@
+/* $NetBSD: mach_intr.c,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Platform-specific interrupt support for the Alchemy parts.
+ *
+ * These boards just use the interrupt controller built into the
+ * Alchemy processors, so we just provide evbmips-compliant wrapper
+ * routines.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: mach_intr.c,v 1.1 2015/04/29 08:32:01 hikaru Exp $");
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/systm.h>
+
+#include <mips/locore.h>
+#include <mips/cavium/octeonvar.h>
+
+void
+evbmips_intr_init(void)
+{
+ octeon_intr_init();
+}
+
+void
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
+{
+
+ octeon_iointr(ipl, pc, ipending);
+}
diff -r 1363f328ad9a -r 1e9fc7ffbbca sys/arch/evbmips/cavium/machdep.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/evbmips/cavium/machdep.c Wed Apr 29 08:32:00 2015 +0000
@@ -0,0 +1,434 @@
+/* $NetBSD: machdep.c,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+
+/*
+ * Copyright 2001, 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
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