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[src/trunk]: src/sys/arch ARM spells the System Control Register SCTLR
details: https://anonhg.NetBSD.org/src/rev/caf29b27fc2e
branches: trunk
changeset: 337774:caf29b27fc2e
user: skrll <skrll%NetBSD.org@localhost>
date: Mon Apr 27 06:54:12 2015 +0000
description:
ARM spells the System Control Register SCTLR
diffstat:
sys/arch/aarch64/include/armreg.h | 6 +++---
sys/arch/arm/arm/core_machdep.c | 6 +++---
sys/arch/arm/arm/cpu_exec.c | 6 +++---
sys/arch/arm/cortex/a9_mpsubr.S | 22 +++++++++++-----------
sys/arch/arm/include/armreg.h | 6 +++---
5 files changed, 23 insertions(+), 23 deletions(-)
diffs (182 lines):
diff -r f6a567a13420 -r caf29b27fc2e sys/arch/aarch64/include/armreg.h
--- a/sys/arch/aarch64/include/armreg.h Mon Apr 27 06:51:40 2015 +0000
+++ b/sys/arch/aarch64/include/armreg.h Mon Apr 27 06:54:12 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.1 2014/08/10 05:47:37 matt Exp $ */
+/* $NetBSD: armreg.h,v 1.2 2015/04/27 06:54:12 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -268,8 +268,8 @@
AARCH64REG_READ_INLINE(rvbar_el1) // Reset Vector Base Address Register
AARCH64REG_WRITE_INLINE(rvbar_el1)
-AARCH64REG_READ_INLINE(sctrl_el1) // System Control Register
-AARCH64REG_WRITE_INLINE(sctrl_el1)
+AARCH64REG_READ_INLINE(sctlr_el1) // System Control Register
+AARCH64REG_WRITE_INLINE(sctlr_el1)
AARCH64REG_READ_INLINE(sp_el0) // Stack Pointer
AARCH64REG_WRITE_INLINE(sp_el0)
diff -r f6a567a13420 -r caf29b27fc2e sys/arch/arm/arm/core_machdep.c
--- a/sys/arch/arm/arm/core_machdep.c Mon Apr 27 06:51:40 2015 +0000
+++ b/sys/arch/arm/arm/core_machdep.c Mon Apr 27 06:54:12 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: core_machdep.c,v 1.7 2014/02/25 21:29:12 matt Exp $ */
+/* $NetBSD: core_machdep.c,v 1.8 2015/04/27 06:54:12 skrll Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@@ -37,7 +37,7 @@
#include <sys/param.h>
-__KERNEL_RCSID(0, "$NetBSD: core_machdep.c,v 1.7 2014/02/25 21:29:12 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: core_machdep.c,v 1.8 2015/04/27 06:54:12 skrll Exp $");
#ifdef _KERNEL_OPT
#include "opt_execfmt.h"
@@ -135,7 +135,7 @@
#ifdef __ARMEB__
if (CPU_IS_ARMV7_P()
|| (CPU_IS_ARMV6_P()
- && (armreg_sctrl_read() & CPU_CONTROL_BEND_ENABLE) == 0)) {
+ && (armreg_sctlr_read() & CPU_CONTROL_BEND_ENABLE) == 0)) {
eh->e_flags |= EF_ARM_BE8;
}
#endif
diff -r f6a567a13420 -r caf29b27fc2e sys/arch/arm/arm/cpu_exec.c
--- a/sys/arch/arm/arm/cpu_exec.c Mon Apr 27 06:51:40 2015 +0000
+++ b/sys/arch/arm/arm/cpu_exec.c Mon Apr 27 06:54:12 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_exec.c,v 1.9 2014/02/20 15:45:20 matt Exp $ */
+/* $NetBSD: cpu_exec.c,v 1.10 2015/04/27 06:54:12 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_exec.c,v 1.9 2014/02/20 15:45:20 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_exec.c,v 1.10 2015/04/27 06:54:12 skrll Exp $");
#include "opt_compat_netbsd.h"
#include "opt_compat_netbsd32.h"
@@ -77,7 +77,7 @@
* If the BE-8 model is supported, CPSR[7] will be clear.
* If the BE-32 model is supported, CPSR[7] will be set.
*/
- register_t ctl = armreg_sctrl_read();
+ register_t ctl = armreg_sctlr_read();
if (((ctl & CPU_CONTROL_BEND_ENABLE) != 0) == be8_p)
return ENOEXEC;
#endif /* __ARMEB__ */
diff -r f6a567a13420 -r caf29b27fc2e sys/arch/arm/cortex/a9_mpsubr.S
--- a/sys/arch/arm/cortex/a9_mpsubr.S Mon Apr 27 06:51:40 2015 +0000
+++ b/sys/arch/arm/cortex/a9_mpsubr.S Mon Apr 27 06:54:12 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: a9_mpsubr.S,v 1.33 2015/04/26 16:22:57 jmcneill Exp $ */
+/* $NetBSD: a9_mpsubr.S,v 1.34 2015/04/27 06:54:12 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -161,12 +161,12 @@
mcr p15, 0, r1, c7, c5, 0 // invalidate I cache
- mrc p15, 0, r2, c1, c0, 0 // SCTRL read
+ mrc p15, 0, r2, c1, c0, 0 // SCTLR read
movw r1, #(CPU_CONTROL_DC_ENABLE|CPU_CONTROL_IC_ENABLE)
bic r2, r2, r1 // clear I+D cache enable
#ifdef __ARMEB__
- // SCTRL.EE determines the endianness of translation table lookups.
+ // SCTLR.EE determines the endianness of translation table lookups.
// So we need to make sure it's set before starting to use the new
// translation tables (which are big endian).
//
@@ -178,7 +178,7 @@
pli [pc, #128]
#endif
- mcr p15, 0, r2, c1, c0, 0 // SCTRL write
+ mcr p15, 0, r2, c1, c0, 0 // SCTLR write
XPUTC(#'F')
dsb // Drain the write buffers.
@@ -230,7 +230,7 @@
// Enable the MMU, etc.
//
XPUTC(#'L')
- mrc p15, 0, r1, c1, c0, 0 // SCTRL read
+ mrc p15, 0, r1, c1, c0, 0 // SCTLR read
movw r3, #:lower16:CPU_CONTROL_SET
#if (CPU_CONTROL_SET & 0xffff0000)
@@ -240,7 +240,7 @@
#if defined(CPU_CONTROL_CLR) && (CPU_CONTROL_CLR != 0)
bic r0, r0, #CPU_CONTROL_CLR
#endif
- //cmp r0, r1 // any changes to SCTRL?
+ //cmp r0, r1 // any changes to SCTLR?
//bxeq ip // no, then return.
pli 1f
@@ -249,7 +249,7 @@
// turn mmu on!
//
mov r0, r0 // fetch instruction cacheline
-1: mcr p15, 0, r0, c1, c0, 0 // SCTRL write
+1: mcr p15, 0, r0, c1, c0, 0 // SCTLR write
// Ensure that the coprocessor has finished turning on the MMU.
//
@@ -489,11 +489,11 @@
#endif /* MULTIPROCESSOR */
//
- // Step 4b, restore SCTRL (enable the data cache)
+ // Step 4b, restore SCTLR (enable the data cache)
//
orr r4, r4, #CPU_CONTROL_IC_ENABLE // enable icache
orr r4, r4, #CPU_CONTROL_DC_ENABLE // enable dcache
- mcr p15, 0, r4, c1, c0, 0 // SCTRL write
+ mcr p15, 0, r4, c1, c0, 0 // SCTLR write
isb
XPUTC(#'-')
@@ -590,11 +590,11 @@
mcr p15, 0, r2, c12, c0, 0 // VBAR set
isb
- mrc p15, 0, r0, c1, c0, 0 // SCTRL read
+ mrc p15, 0, r0, c1, c0, 0 // SCTLR read
#ifdef MULTIPROCESSOR
bic r0, r0, #CPU_CONTROL_VECRELOC // use VBAR
#endif
- mcr p15, 0, r0, c1, c0, 0 // SCTRL write
+ mcr p15, 0, r0, c1, c0, 0 // SCTLR write
dsb
isb
#endif
diff -r f6a567a13420 -r caf29b27fc2e sys/arch/arm/include/armreg.h
--- a/sys/arch/arm/include/armreg.h Mon Apr 27 06:51:40 2015 +0000
+++ b/sys/arch/arm/include/armreg.h Mon Apr 27 06:54:12 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.102 2014/11/27 04:07:13 matt Exp $ */
+/* $NetBSD: armreg.h,v 1.103 2015/04/27 06:54:12 skrll Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -887,8 +887,8 @@
ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
/* cp15 c1 registers */
-ARMREG_READ_INLINE(sctrl, "p15,0,%0,c1,c0,0") /* System Control Register */
-ARMREG_WRITE_INLINE(sctrl, "p15,0,%0,c1,c0,0") /* System Control Register */
+ARMREG_READ_INLINE(sctlr, "p15,0,%0,c1,c0,0") /* System Control Register */
+ARMREG_WRITE_INLINE(sctlr, "p15,0,%0,c1,c0,0") /* System Control Register */
ARMREG_READ_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */
ARMREG_WRITE_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */
ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */
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