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[src/trunk]: src/sys/arch/mips/mips Sprinkle MFC0_HAZARD everywhere.
details: https://anonhg.NetBSD.org/src/rev/22fb59a74881
branches: trunk
changeset: 346235:22fb59a74881
user: maya <maya%NetBSD.org@localhost>
date: Sat Jul 02 19:40:57 2016 +0000
description:
Sprinkle MFC0_HAZARD everywhere.
ok dholland@
diffstat:
sys/arch/mips/mips/locore.S | 3 ++-
sys/arch/mips/mips/mipsX_subr.S | 31 +++++++++++++++++++++++++++----
2 files changed, 29 insertions(+), 5 deletions(-)
diffs (197 lines):
diff -r fe7a8674a73c -r 22fb59a74881 sys/arch/mips/mips/locore.S
--- a/sys/arch/mips/mips/locore.S Sat Jul 02 18:29:59 2016 +0000
+++ b/sys/arch/mips/mips/locore.S Sat Jul 02 19:40:57 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.199 2016/07/02 18:29:59 maya Exp $ */
+/* $NetBSD: locore.S,v 1.200 2016/07/02 19:40:57 maya Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -157,6 +157,7 @@
#endif /* HPCMIPS_L1CACHE_DISABLE */
#else
mfc0 t0, MIPS_COP_0_STATUS
+ MFC0_HAZARD
#ifdef _LP64
or t0, MIPS_SR_KX # turn on XKSEG and XKPHYS
#endif
diff -r fe7a8674a73c -r 22fb59a74881 sys/arch/mips/mips/mipsX_subr.S
--- a/sys/arch/mips/mips/mipsX_subr.S Sat Jul 02 18:29:59 2016 +0000
+++ b/sys/arch/mips/mips/mipsX_subr.S Sat Jul 02 19:40:57 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsX_subr.S,v 1.62 2015/06/11 07:30:10 matt Exp $ */
+/* $NetBSD: mipsX_subr.S,v 1.63 2016/07/02 19:40:57 maya Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -134,6 +134,12 @@
#include "assym.h"
+#if defined(MIPS1) || defined(MIPS2) || defined(MIPS3)
+#define MFC0_HAZARD nop
+#else
+#define MFC0_HAZARD /* nothing */
+#endif
+
#ifdef _LP64
#define RESET_EXCEPTION_LEVEL_DISABLE_INTERRUPTS(reg) \
li reg, MIPS_SR_KX; mtc0 reg, MIPS_COP_0_STATUS
@@ -1080,6 +1086,7 @@
* Now we can clear exception level since no interrupts can be delivered
*/
mfc0 v1, MIPS_COP_0_STATUS
+ MFC0_HAZARD
and v0, v1, MIPS_SR_EXL # grab exception level bit
xor v0, v1 # clear it
mtc0 v0, MIPS_COP_0_STATUS # write new status
@@ -1098,6 +1105,7 @@
#if defined(PARANOIA)
mfc0 t0, MIPS_COP_0_STATUS # verify INT_IE is still set
+ MFC0_HAZARD
and t0, MIPS_SR_INT_IE
#if defined(MIPS32) || defined(MIPS32R2) || defined(MIPS64) || defined(MIPS64R2)
teqi t0, 0
@@ -1112,6 +1120,7 @@
beqz a0, 4f # nope
nop
mfc0 v0, MIPS_COP_0_CAUSE # grab the pending softints
+ MFC0_HAZARD
and a0, v0 # are softints pending
beqz a0, 4f # nope
nop
@@ -1146,6 +1155,7 @@
di v0 # disable interrupts
#else
mfc0 v0, MIPS_COP_0_STATUS # read it
+ MFC0_HAZARD
xor v0, MIPS_SR_INT_IE # disable interrupts
mtc0 v0, MIPS_COP_0_STATUS # write it
#endif
@@ -1175,6 +1185,7 @@
#ifdef PARANOIA
mfc0 v0, MIPS_COP_0_STATUS
+ MFC0_HAZARD
or v0, MIPS_SR_INT_IE
5: bne v0, s1, 5b
nop
@@ -1220,6 +1231,7 @@
/* If this was in a branch delay slot, take the slow path. */
mfc0 v0, MIPS_COP_0_CAUSE
+ MFC0_HAZARD
bltz v0, MIPSX(user_gen_exception_common)
nop
@@ -1228,6 +1240,7 @@
* this since the instruction actually got read.
*/
_MFC0 v0, MIPS_COP_0_EXC_PC
+ MFC0_HAZARD
INT_L AT, 0(v0)
/*
@@ -1242,6 +1255,7 @@
* Advance the PC (don't want to restart at the rdhwr).
*/
_MFC0 v0, MIPS_COP_0_EXC_PC
+ MFC0_HAZARD
PTR_ADDIU v0, 4
_MTC0 v0, MIPS_COP_0_EXC_PC
COP0_SYNC
@@ -1444,6 +1458,7 @@
*/
mfc0 v1, MIPS_COP_0_STATUS
#ifdef NOFPU
+ MFC0_HAZARD
and v0, v1, MIPS_SR_KSU_MASK|MIPS_SR_EXL
xor v0, v1 # clear the bits
#else
@@ -1487,6 +1502,7 @@
nop
#endif
mfc0 a0, MIPS_COP_0_CAUSE # grab the pending softints
+ MFC0_HAZARD
and a0, MIPS_SOFT_INT_MASK # are there softints pending
beqz a0, 4f # nope
nop
@@ -1501,6 +1517,7 @@
di # disable interrupts
#else
mfc0 v1, MIPS_COP_0_STATUS
+ MFC0_HAZARD
and v0, v1, MIPS_SR_INT_IE # clear interrupt enable
xor v0, v1
mtc0 v0, MIPS_COP_0_STATUS # interrupts are disabled
@@ -1539,6 +1556,7 @@
ei # enable interrupts
#else
mfc0 t0, MIPS_COP_0_STATUS #
+ MFC0_HAZARD
or t0, MIPS_SR_INT_IE # enable interrupts
DYNAMIC_STATUS_MASK(t0, t1) # machine dependent masking
mtc0 t0, MIPS_COP_0_STATUS # enable interrupts (spl0)
@@ -1838,9 +1856,7 @@
COP0_SYNC
mfc0 k0, MIPS_COP_0_TLB_INDEX
-#ifdef MIPS3
- nop
-#endif
+ MFC0_HAZARD
bltz k0, _C_LABEL(MIPSX(kern_gen_exception)) # ASSERT(TLB entry exists)
nop # - delay slot -
@@ -2124,6 +2140,7 @@
tlbp # probe the entry in question
COP0_SYNC
mfc0 v0, MIPS_COP_0_TLB_INDEX # see what we got
+ MFC0_HAZARD
bltz v0, 1f # index < 0 then skip
li t1, MIPS_KSEG0_START # invalid address
PTR_SLL v0, PGSHIFT + 1 # PAGE_SHIFT + 1
@@ -2183,10 +2200,12 @@
tlbr # obtain an entry
COP0_SYNC
_MFC0 a0, MIPS_COP_0_TLB_LO1
+ MFC0_HAZARD
and a0, MIPS3_PG_G # check to see it has G bit
bnez a0, 2f # yep, skip this one.
nop
_MFC0 a0, MIPS_COP_0_TLB_HI # get VA and ASID
+ MFC0_HAZARD
and a0, MIPS3_PG_ASID # focus on ASID
sltu a3, a0, a1 # asid < base?
bnez a3, 2f # yes, skip this entry.
@@ -2246,6 +2265,7 @@
tlbr # obtain an entry
COP0_SYNC
_MFC0 a0, MIPS_COP_0_TLB_LO1
+ MFC0_HAZARD
and a0, MIPS3_PG_G # check to see it has G bit
beqz a0, 2f # no, skip this entry
nop
@@ -2359,11 +2379,13 @@
tlbr # obtain an entry
COP0_SYNC
_MFC0 t0, MIPS_COP_0_TLB_LO1
+ MFC0_HAZARD
and t0, MIPS3_PG_G # check to see it has G bit
bnez t0, 4f # yep, skip this one.
nop
_MFC0 t0, MIPS_COP_0_TLB_HI # get VA and ASID
+ MFC0_HAZARD
and t0, a1 # focus on ASID
srl a2, t0, 3 + LONG_SCALESHIFT # drop low 5 or 6 bits
@@ -2422,6 +2444,7 @@
COP0_SYNC
mfc0 v0, MIPS_COP_0_TLB_INDEX # was it in the TLB?
+ MFC0_HAZARD
bltz v0, 1f # nope
nop
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