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[src/trunk]: src/sys/arch/mips/mips Trailing whitespace
details: https://anonhg.NetBSD.org/src/rev/5b2435a219e4
branches: trunk
changeset: 346395:5b2435a219e4
user: skrll <skrll%NetBSD.org@localhost>
date: Mon Jul 11 18:54:32 2016 +0000
description:
Trailing whitespace
diffstat:
sys/arch/mips/mips/mipsX_subr.S | 16 ++++++++--------
sys/arch/mips/mips/mips_machdep.c | 24 ++++++++++++------------
sys/arch/mips/mips/trap.c | 20 ++++++++++----------
3 files changed, 30 insertions(+), 30 deletions(-)
diffs (260 lines):
diff -r 818833b47d2b -r 5b2435a219e4 sys/arch/mips/mips/mipsX_subr.S
--- a/sys/arch/mips/mips/mipsX_subr.S Mon Jul 11 18:07:33 2016 +0000
+++ b/sys/arch/mips/mips/mipsX_subr.S Mon Jul 11 18:54:32 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsX_subr.S,v 1.69 2016/07/11 18:07:33 matt Exp $ */
+/* $NetBSD: mipsX_subr.S,v 1.70 2016/07/11 19:00:04 skrll Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -361,7 +361,7 @@
* Loongson2 processors don't have separate tlbmiss and xtlbmiss handlers;
* so we have to check for useg addresses in tlb_miss. The good news is that
* we can use 64 intructions form tlbmiss instead of 32.
- *
+ *
*----------------------------------------------------------------------------
*/
#ifdef MIPS3_LOONGSON2
@@ -1020,7 +1020,7 @@
* Clear exception level.
*/
li v0, ~(MIPS_SR_EXL|MIPS3_SR_NMI)
- and v0, a0 # zero NMI/EXL bits
+ and v0, a0 # zero NMI/EXL bits
mtc0 v0, MIPS_COP_0_STATUS # update.
COP0_SYNC
#ifdef MIPS3
@@ -1858,7 +1858,7 @@
PTR_LA k1, _C_LABEL(pmap_limits)
PTR_L k1, PMAP_LIMITS_VIRTUAL_END(k1)
PTR_SUBU k1, k0
- blez k1, _C_LABEL(MIPSX(kern_gen_exception)) # full trap processing
+ blez k1, _C_LABEL(MIPSX(kern_gen_exception)) # full trap processing
nop
PTR_LA k1, _C_LABEL(pmap_kern_segtab)
#ifdef _LP64
@@ -1872,7 +1872,7 @@
#endif
_MFC0 k0, MIPS_COP_0_BAD_VADDR # get the fault address (again)
PTR_L k1, (k1) # load segtab address
- beqz k1, _C_LABEL(MIPSX(kern_gen_exception))
+ beqz k1, _C_LABEL(MIPSX(kern_gen_exception))
nop
#endif
#ifdef MIPSNNR2
@@ -1885,7 +1885,7 @@
#endif
_MFC0 k0, MIPS_COP_0_BAD_VADDR # get the fault address (again)
PTR_L k1, (k1) # load page table address
- beqz k1, _C_LABEL(MIPSX(kern_gen_exception))
+ beqz k1, _C_LABEL(MIPSX(kern_gen_exception))
nop
#ifdef MIPSNNR2
_EXT k0, k0, PGSHIFT, PTPLENGTH
@@ -2084,7 +2084,7 @@
*/
LEAF(MIPSX(tlb_update_addr))
#ifdef MIPSNNR2
- di ta0 # Disable interrupts
+ di ta0 # Disable interrupts
#else
mfc0 ta0, MIPS_COP_0_STATUS # Save the status register.
mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts
@@ -2710,7 +2710,7 @@
#if !defined(ENABLE_MIPS_16KB_PAGE) && !defined(ENABLE_MIPS_8KB_PAGE)
INT_L a1, L_MD_UPTE_0(a0) # a1 = upte[0]
#if (PGSHIFT & 1)
- INT_ADD a2, a1, MIPS3_PG_NEXT # a2 = upper half
+ INT_ADD a2, a1, MIPS3_PG_NEXT # a2 = upper half
#else
INT_L a2, L_MD_UPTE_1(a0) # a2 = upte[1]
#endif
diff -r 818833b47d2b -r 5b2435a219e4 sys/arch/mips/mips/mips_machdep.c
--- a/sys/arch/mips/mips/mips_machdep.c Mon Jul 11 18:07:33 2016 +0000
+++ b/sys/arch/mips/mips/mips_machdep.c Mon Jul 11 18:54:32 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_machdep.c,v 1.271 2016/07/11 16:15:36 matt Exp $ */
+/* $NetBSD: mips_machdep.c,v 1.272 2016/07/11 18:56:41 skrll Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -111,7 +111,7 @@
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.271 2016/07/11 16:15:36 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.272 2016/07/11 18:56:41 skrll Exp $");
#define __INTR_PRIVATE
#include "opt_cputype.h"
@@ -365,7 +365,7 @@
{ 0, MIPS_TX3900, MIPS_REV_TX3927, -1, CPU_ARCH_MIPS1, 64,
CPU_MIPS_NO_LLSC, 0, 0, "Toshiba TX3927 CPU" },
{ 0, MIPS_R5000, -1, -1, CPU_ARCH_MIPS4, 48,
- CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0,
+ CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0,
"MIPS R5000 CPU" },
{ 0, MIPS_RM5200, -1, -1, CPU_ARCH_MIPS4, 48,
CPU_MIPS_R4K_MMU | CPU_MIPS_CAUSE_IV | CPU_MIPS_DOUBLE_COUNT |
@@ -380,7 +380,7 @@
MIPS_NOT_SUPP | CPU_MIPS_CAUSE_IV | CPU_MIPS_DOUBLE_COUNT |
CPU_MIPS_USE_WAIT, 0, 0, "QED RM7000 CPU" },
- /*
+ /*
* IDT RC32300 core is a 32 bit MIPS2 processor with
* MIPS3/MIPS4 extensions. It has an R4000-style TLB,
* while all registers are 32 bits and any 64 bit
@@ -415,7 +415,7 @@
CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0,
"Toshiba TX4900 CPU" },
- /*
+ /*
* ICT Loongson2 is a MIPS64 CPU with a few quirks. For some reason
* the virtual aliases present with 4KB pages make the caches misbehave
* so we make all accesses uncached. With 16KB pages, no virtual
@@ -1318,7 +1318,7 @@
mips3_vector_init(splsw);
mips_locoresw = mips3_locoresw;
break;
-
+
#endif /* MIPS3 */
#if defined(MIPS32)
case CPU_ARCH_MIPS32:
@@ -1528,7 +1528,7 @@
mci->mci_picache_line_size, waynames[mci->mci_picache_ways],
opts->mips_num_tlb_entries);
else
- aprint_normal_dev(dev, "%d TLB entries\n",
+ aprint_normal_dev(dev, "%d TLB entries\n",
opts->mips_num_tlb_entries);
if (mci->mci_pdcache_size)
aprint_normal_dev(dev, "%dKB/%dB %s %s Data cache\n",
@@ -2140,7 +2140,7 @@
/*
* If this segment doesn't overlap the freelist
* at all, skip it.
- */
+ */
if (segstart >= flp[i].fl_end
|| segend <= flp[i].fl_start)
continue;
@@ -2218,12 +2218,12 @@
break;
}
}
-
+
/*
* Now we give this segment to uvm.
*/
printf("adding %#"PRIxPADDR" @ %#"PRIxPADDR" to freelist %d\n",
-
+
segend - segstart, segstart, freelist);
paddr_t first = atop(segstart);
paddr_t last = atop(segend);
@@ -2237,7 +2237,7 @@
}
}
-/*
+/*
* Start a new LWP
*/
void
@@ -2255,7 +2255,7 @@
}
#ifdef COMPAT_NETBSD32
-/*
+/*
* Start a new LWP
*/
void
diff -r 818833b47d2b -r 5b2435a219e4 sys/arch/mips/mips/trap.c
--- a/sys/arch/mips/mips/trap.c Mon Jul 11 18:07:33 2016 +0000
+++ b/sys/arch/mips/mips/trap.c Mon Jul 11 18:54:32 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.240 2016/07/11 16:15:36 matt Exp $ */
+/* $NetBSD: trap.c,v 1.241 2016/07/11 18:54:32 skrll Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -39,7 +39,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.240 2016/07/11 16:15:36 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.241 2016/07/11 18:54:32 skrll Exp $");
#include "opt_cputype.h" /* which mips CPU levels do we support? */
#include "opt_ddb.h"
@@ -190,24 +190,24 @@
int n, sz = sizeof(strbuf);
n = snprintf(str, sz, "pid %d(%s): ", p->p_pid, p->p_comm);
- sz -= n;
+ sz -= n;
str += n;
n = snprintf(str, sz, "trap: cpu%d, %s in %s mode\n",
cpu_number(), trap_names[TRAPTYPE(cause)],
USERMODE(status) ? "user" : "kernel");
- sz -= n;
+ sz -= n;
str += n;
n = snprintf(str, sz, "status=%#x, cause=%#x, epc=%#"
PRIxVADDR ", vaddr=%#" PRIxVADDR "\n",
status, cause, pc, vaddr);
- sz -= n;
+ sz -= n;
str += n;
if (USERMODE(status)) {
KASSERT(tf == utf);
n = snprintf(str, sz, "frame=%p usp=%#" PRIxREGISTER
" ra=%#" PRIxREGISTER "\n",
tf, tf->tf_regs[_R_SP], tf->tf_regs[_R_RA]);
- sz -= n;
+ sz -= n;
str += n;
} else {
n = snprintf(str, sz, "tf=%p ksp=%p ra=%#"
@@ -216,7 +216,7 @@
? (void*)(uintptr_t)tf->tf_regs[_R_SP]
: tf+1,
tf->tf_regs[_R_RA], tf->tf_ppl);
- sz -= n;
+ sz -= n;
str += n;
}
printf("%s", strbuf);
@@ -261,7 +261,7 @@
kpreempt_disable();
pt_entry_t * const ptep = pmap_pte_lookup(pmap, vaddr);
- if (!ptep)
+ if (!ptep)
panic("%ctlbmod: %#"PRIxVADDR": no pte",
user_p ? 'u' : 'k', vaddr);
pt_entry_t pte = *ptep;
@@ -922,7 +922,7 @@
/*
* Find the beginning of the current subroutine by scanning backwards
* from the current PC for the end of the previous subroutine.
- *
+ *
* XXX This won't work well because nowadays gcc is so aggressive
* as to reorder instruction blocks for branch-predict.
* (i.e. 'jr ra' wouldn't indicate the end of subroutine)
@@ -1079,7 +1079,7 @@
}
} else {
finish:
- (*printfn)("User-level: pid %d.%d\n",
+ (*printfn)("User-level: pid %d.%d\n",
curlwp->l_proc->p_pid, curlwp->l_lid);
}
}
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