[src/trunk]: src/sys/arch/arm/nvidia disable SATA sleep feature

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/85430b8e8b6b
branches:  trunk
changeset: 341038:85430b8e8b6b
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Thu Oct 15 09:04:35 2015 +0000

description:
disable SATA sleep feature

diffstat:

 sys/arch/arm/nvidia/tegra_ahcisata.c    |  18 ++++++++++++++++--
 sys/arch/arm/nvidia/tegra_ahcisatareg.h |  10 +++++++++-
 2 files changed, 25 insertions(+), 3 deletions(-)

diffs (63 lines):

diff -r 9f2fdef2bede -r 85430b8e8b6b sys/arch/arm/nvidia/tegra_ahcisata.c
--- a/sys/arch/arm/nvidia/tegra_ahcisata.c      Thu Oct 15 07:14:56 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_ahcisata.c      Thu Oct 15 09:04:35 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_ahcisata.c,v 1.6 2015/05/24 22:30:22 jmcneill Exp $ */
+/* $NetBSD: tegra_ahcisata.c,v 1.7 2015/10/15 09:04:35 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
 #include "locators.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.6 2015/05/24 22:30:22 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.7 2015/10/15 09:04:35 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -129,6 +129,20 @@
        const u_int gen2_tx_amp = 0x18;
        const u_int gen2_tx_peak = 0x0a;
 
+       /* Set RX idle detection source and disable RX idle detection interrupt */
+       tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG,
+           TEGRA_SATA_AUX_MISC_CNTL_1_AUX_OR_CORE_IDLE_STATUS_SEL, 0);
+       tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_RX_STAT_INT_REG,
+           TEGRA_SATA_AUX_RX_STAT_INT_SATA_RX_STAT_INT_DISABLE, 0);
+
+       /* Prevent automatic OOB sequence when coming out of reset */
+       tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG,
+           0, TEGRA_SATA_AUX_MISC_CNTL_1_OOB_ON_POR);
+
+       /* Disable device sleep */
+       tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG,
+           0, TEGRA_SATA_AUX_MISC_CNTL_1_SDS_SUPPORT);
+
        /* Enable IFPS device block */
        tegra_reg_set_clear(bst, bsh, TEGRA_SATA_CONFIGURATION_REG,
            TEGRA_SATA_CONFIGURATION_EN_FPCI, 0);
diff -r 9f2fdef2bede -r 85430b8e8b6b sys/arch/arm/nvidia/tegra_ahcisatareg.h
--- a/sys/arch/arm/nvidia/tegra_ahcisatareg.h   Thu Oct 15 07:14:56 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_ahcisatareg.h   Thu Oct 15 09:04:35 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_ahcisatareg.h,v 1.1 2015/05/15 17:43:35 jmcneill Exp $ */
+/* $NetBSD: tegra_ahcisatareg.h,v 1.2 2015/10/15 09:04:35 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -53,6 +53,14 @@
 #define TEGRA_T_SATA0_CFG9_BASE_ADDRESS                        __BITS(31,13) 
 #define TEGRA_T_SATA0_CFG9_SPACE_TYPE                  __BIT(0)
 
+#define TEGRA_SATA_AUX_MISC_CNTL_1_REG         0x1108
+#define TEGRA_SATA_AUX_MISC_CNTL_1_AUX_OR_CORE_IDLE_STATUS_SEL __BIT(18)
+#define TEGRA_SATA_AUX_MISC_CNTL_1_SDS_SUPPORT                 __BIT(13)
+#define TEGRA_SATA_AUX_MISC_CNTL_1_OOB_ON_POR                  __BIT(7)
+
+#define TEGRA_SATA_AUX_RX_STAT_INT_REG         0x110c
+#define TEGRA_SATA_AUX_RX_STAT_INT_SATA_RX_STAT_INT_DISABLE    __BIT(2)
+
 #define TEGRA_T_SATA0_BKDOOR_CC_REG            0x14a4
 #define TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE             __BITS(31,16)
 #define TEGRA_T_SATA0_BKDOOR_CC_PROG_IF                        __BITS(15,8)