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[src/trunk]: src/sys/arch reduce the number of magic numbers in phy setup, pu...



details:   https://anonhg.NetBSD.org/src/rev/f95b732e2259
branches:  trunk
changeset: 341144:f95b732e2259
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Wed Oct 21 10:43:09 2015 +0000

description:
reduce the number of magic numbers in phy setup, pull settings from device properties instead.

diffstat:

 sys/arch/arm/nvidia/tegra_ehci.c      |  67 +++++++++++++++++++++++++++++-----
 sys/arch/evbarm/tegra/tegra_machdep.c |  19 ++++++++-
 2 files changed, 74 insertions(+), 12 deletions(-)

diffs (181 lines):

diff -r 5d44df89aa5e -r f95b732e2259 sys/arch/arm/nvidia/tegra_ehci.c
--- a/sys/arch/arm/nvidia/tegra_ehci.c  Wed Oct 21 09:25:16 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_ehci.c  Wed Oct 21 10:43:09 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_ehci.c,v 1.7 2015/05/22 06:27:17 skrll Exp $ */
+/* $NetBSD: tegra_ehci.c,v 1.8 2015/10/21 10:43:09 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
 #include "locators.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_ehci.c,v 1.7 2015/05/22 06:27:17 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_ehci.c,v 1.8 2015/10/21 10:43:09 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -63,8 +63,19 @@
        u_int                   sc_port;
 
        struct tegra_gpio_pin   *sc_pin_vbus;
+       uint8_t                 sc_hssync_start_delay;
+       uint8_t                 sc_idle_wait_delay;
+       uint8_t                 sc_elastic_limit;
+       uint8_t                 sc_term_range_adj;
+       uint8_t                 sc_xcvr_setup;
+       uint8_t                 sc_xcvr_lsfslew;
+       uint8_t                 sc_xcvr_lsrslew;
+       uint8_t                 sc_hssquelch_level;
+       uint8_t                 sc_hsdiscon_level;
+       uint8_t                 sc_xcvr_hsslew;
 };
 
+static int     tegra_ehci_parse_properties(struct tegra_ehci_softc *);
 static void    tegra_ehci_utmip_init(struct tegra_ehci_softc *);
 static int     tegra_ehci_port_status(struct ehci_softc *sc, uint32_t v,
                    int i);
@@ -113,6 +124,9 @@
        aprint_naive("\n");
        aprint_normal(": USB%d\n", loc->loc_port + 1);
 
+       if (tegra_ehci_parse_properties(sc) != 0)
+               return;
+
        tegra_car_periph_usb_enable(sc->sc_port);
        delay(2);
 
@@ -151,6 +165,33 @@
        sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
 }
 
+static int
+tegra_ehci_parse_properties(struct tegra_ehci_softc *sc)
+{
+#define PROPGET(k, v)  \
+       if (prop_dictionary_get_uint8(prop, (k), (v)) == false) {       \
+               aprint_error_dev(sc->sc.sc_dev,                         \
+                   "missing property '%s'\n", (k));                    \
+               return EIO;                                             \
+       }
+
+       prop_dictionary_t prop = device_properties(sc->sc.sc_dev);
+
+       PROPGET("nvidia,hssync-start-delay", &sc->sc_hssync_start_delay);
+       PROPGET("nvidia,idle-wait-delay", &sc->sc_idle_wait_delay);
+       PROPGET("nvidia,elastic-limit", &sc->sc_elastic_limit);
+       PROPGET("nvidia,term-range-adj", &sc->sc_term_range_adj);
+       PROPGET("nvidia,xcvr-setup", &sc->sc_xcvr_setup);
+       PROPGET("nvidia,xcvr-lsfslew", &sc->sc_xcvr_lsfslew);
+       PROPGET("nvidia,xcvr-lsrslew", &sc->sc_xcvr_lsrslew);
+       PROPGET("nvidia,hssquelch-level", &sc->sc_hssquelch_level);
+       PROPGET("nvidia,hsdiscon-level", &sc->sc_hsdiscon_level);
+       PROPGET("nvidia,xcvr-hsslew", &sc->sc_xcvr_hsslew);
+
+       return 0;
+#undef PROPGET
+}
+
 static void
 tegra_ehci_init(struct ehci_softc *esc)
 {
@@ -215,18 +256,21 @@
        tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG,
            __SHIFTIN(4, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP) |
            __SHIFTIN(3, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB) |
-           __SHIFTIN(8, TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB),
+           __SHIFTIN(sc->sc_xcvr_hsslew,
+                     TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB),
            TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP |
            TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB |
            TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB);
        tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG,
-           __SHIFTIN(7, TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ),
+           __SHIFTIN(sc->sc_term_range_adj,
+                     TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ),
            TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ);
 
        if (sc->sc_port == 0) {
                tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG0_REG,
                    TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL_MSB |
-                   __SHIFTIN(2, TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL),
+                   __SHIFTIN(sc->sc_hsdiscon_level,
+                             TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL),
                    TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL); 
        }
 
@@ -237,12 +281,12 @@
 
        /* BIAS cell power down lag */
        tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG,
-           __SHIFTIN(6, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT),
+           __SHIFTIN(5, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT),
            TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT);
 
        /* Debounce config */
        tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_REG,
-           __SHIFTIN(0x73f4, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A),
+           __SHIFTIN(0x7530, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A),
            TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A);
 
        /* Transmit signal preamble config */
@@ -259,12 +303,15 @@
 
        /* High speed receive config */
        tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG0_REG,
-           __SHIFTIN(17, TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT) |
-           __SHIFTIN(16, TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT),
+           __SHIFTIN(sc->sc_idle_wait_delay,
+                     TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT) |
+           __SHIFTIN(sc->sc_elastic_limit,
+                     TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT),
            TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT |
            TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT);
        tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG1_REG,
-           __SHIFTIN(9, TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY),
+           __SHIFTIN(sc->sc_hssync_start_delay,
+                     TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY),
            TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY);
 
        /* Start crystal clock */
diff -r 5d44df89aa5e -r f95b732e2259 sys/arch/evbarm/tegra/tegra_machdep.c
--- a/sys/arch/evbarm/tegra/tegra_machdep.c     Wed Oct 21 09:25:16 2015 +0000
+++ b/sys/arch/evbarm/tegra/tegra_machdep.c     Wed Oct 21 10:43:09 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_machdep.c,v 1.21 2015/10/19 22:00:09 jmcneill Exp $ */
+/* $NetBSD: tegra_machdep.c,v 1.22 2015/10/21 10:43:09 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_machdep.c,v 1.21 2015/10/19 22:00:09 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_machdep.c,v 1.22 2015/10/21 10:43:09 jmcneill Exp $");
 
 #include "opt_tegra.h"
 #include "opt_machdep.h"
@@ -436,6 +436,21 @@
                        prop_dictionary_set_cstring(dict, "debug", debug);
        }
 
+#ifdef SOC_TEGRA124
+       if (device_is_a(self, "ehci")) {
+               prop_dictionary_set_uint8(dict, "nvidia,hssync-start-delay", 0);
+               prop_dictionary_set_uint8(dict, "nvidia,idle-wait-delay", 17);
+               prop_dictionary_set_uint8(dict, "nvidia,elastic-limit", 16);
+               prop_dictionary_set_uint8(dict, "nvidia,term-range-adj", 6);
+               prop_dictionary_set_uint8(dict, "nvidia,xcvr-setup", 9);
+               prop_dictionary_set_uint8(dict, "nvidia,xcvr-lsfslew", 0);
+               prop_dictionary_set_uint8(dict, "nvidia,xcvr-lsrslew", 3);
+               prop_dictionary_set_uint8(dict, "nvidia,hssquelch-level", 2);
+               prop_dictionary_set_uint8(dict, "nvidia,hsdiscon-level", 5);
+               prop_dictionary_set_uint8(dict, "nvidia,xcvr-hsslew", 12);
+       }
+#endif
+
 #ifdef BOARD_JETSONTK1
        if (device_is_a(self, "sdhc")
            && device_is_a(device_parent(self), "tegraio")) {



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