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[src/trunk]: src/sys/dev/pci refactor: separate TX, RX queue variables from w...
details: https://anonhg.NetBSD.org/src/rev/d059c53b5281
branches: trunk
changeset: 340966:d059c53b5281
user: knakahara <knakahara%NetBSD.org@localhost>
date: Tue Oct 13 08:08:03 2015 +0000
description:
refactor: separate TX, RX queue variables from wm_softc (without mutex)
diffstat:
sys/dev/pci/if_wm.c | 717 +++++++++++++++++++++++++++++----------------------
1 files changed, 403 insertions(+), 314 deletions(-)
diffs (truncated from 1620 to 300 lines):
diff -r 0bc73fdaa537 -r d059c53b5281 sys/dev/pci/if_wm.c
--- a/sys/dev/pci/if_wm.c Tue Oct 13 08:03:59 2015 +0000
+++ b/sys/dev/pci/if_wm.c Tue Oct 13 08:08:03 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wm.c,v 1.355 2015/10/13 08:03:59 knakahara Exp $ */
+/* $NetBSD: if_wm.c,v 1.356 2015/10/13 08:08:03 knakahara Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -83,7 +83,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.355 2015/10/13 08:03:59 knakahara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.356 2015/10/13 08:08:03 knakahara Exp $");
#ifdef _KERNEL_OPT
#include "opt_net_mpsafe.h"
@@ -94,6 +94,7 @@
#include <sys/callout.h>
#include <sys/mbuf.h>
#include <sys/malloc.h>
+#include <sys/kmem.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#include <sys/ioctl.h>
@@ -195,16 +196,16 @@
#define WM_IFQUEUELEN 256
#define WM_TXQUEUELEN_MAX 64
#define WM_TXQUEUELEN_MAX_82547 16
-#define WM_TXQUEUELEN(sc) ((sc)->sc_txnum)
-#define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1)
-#define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8)
+#define WM_TXQUEUELEN(txq) ((txq)->txq_num)
+#define WM_TXQUEUELEN_MASK(txq) (WM_TXQUEUELEN(txq) - 1)
+#define WM_TXQUEUE_GC(txq) (WM_TXQUEUELEN(txq) / 8)
#define WM_NTXDESC_82542 256
#define WM_NTXDESC_82544 4096
-#define WM_NTXDESC(sc) ((sc)->sc_ntxdesc)
-#define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1)
-#define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t))
-#define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc))
-#define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc))
+#define WM_NTXDESC(txq) ((txq)->txq_ndesc)
+#define WM_NTXDESC_MASK(txq) (WM_NTXDESC(txq) - 1)
+#define WM_TXDESCSIZE(txq) (WM_NTXDESC(txq) * sizeof(wiseman_txdesc_t))
+#define WM_NEXTTX(txq, x) (((x) + 1) & WM_NTXDESC_MASK(txq))
+#define WM_NEXTTXS(txq, x) (((x) + 1) & WM_TXQUEUELEN_MASK(txq))
#define WM_MAXTXDMA (2 * round_page(IP_MAXPACKET)) /* for TSO */
@@ -261,6 +262,74 @@
36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140
};
+struct wm_softc;
+
+struct wm_txqueue {
+ /* XXX should move tx_lock here. */
+
+ struct wm_softc *txq_sc;
+
+ /* Software state for the transmit descriptors. */
+ int txq_num; /* must be a power of two */
+ struct wm_txsoft txq_soft[WM_TXQUEUELEN_MAX];
+
+ /* TX control data structures. */
+ int txq_ndesc; /* must be a power of two */
+ txdescs_t *txq_descs_u;
+ bus_dmamap_t txq_desc_dmamap; /* control data DMA map */
+ bus_dma_segment_t txq_desc_seg; /* control data segment */
+ int txq_desc_rseg; /* real number of control segment */
+ size_t txq_desc_size; /* control data size */
+#define txq_desc_dma txq_desc_dmamap->dm_segs[0].ds_addr
+#define txq_descs txq_descs_u->sctxu_txdescs
+#define txq_nq_descs txq_descs_u->sctxu_nq_txdescs
+
+ bus_addr_t txq_tdt_reg; /* offset of TDT register */
+
+ int txq_free; /* number of free Tx descriptors */
+ int txq_next; /* next ready Tx descriptor */
+
+ int txq_sfree; /* number of free Tx jobs */
+ int txq_snext; /* next free Tx job */
+ int txq_sdirty; /* dirty Tx jobs */
+
+ /* These 4 variables are used only on the 82547. */
+ int txq_fifo_size; /* Tx FIFO size */
+ int txq_fifo_head; /* current head of FIFO */
+ uint32_t txq_fifo_addr; /* internal address of start of FIFO */
+ int txq_fifo_stall; /* Tx FIFO is stalled */
+
+ /* XXX which event counter is required? */
+};
+
+struct wm_rxqueue {
+ /* XXX should move rx_lock here. */
+
+ struct wm_softc *rxq_sc;
+
+ /* Software state for the receive descriptors. */
+ wiseman_rxdesc_t *rxq_descs;
+
+ /* RX control data structures. */
+ struct wm_rxsoft rxq_soft[WM_NRXDESC];
+ bus_dmamap_t rxq_desc_dmamap; /* control data DMA map */
+ bus_dma_segment_t rxq_desc_seg; /* control data segment */
+ int rxq_desc_rseg; /* real number of control segment */
+ size_t rxq_desc_size; /* control data size */
+#define rxq_desc_dma rxq_desc_dmamap->dm_segs[0].ds_addr
+
+ bus_addr_t rxq_rdt_reg; /* offset of RDT register */
+
+ int rxq_ptr; /* next ready Rx descriptor/queue ent */
+ int rxq_discard;
+ int rxq_len;
+ struct mbuf *rxq_head;
+ struct mbuf *rxq_tail;
+ struct mbuf **rxq_tailp;
+
+ /* XXX which event counter is required? */
+};
+
/*
* Software state per device.
*/
@@ -319,29 +388,11 @@
int sc_ich8_flash_bank_size;
int sc_nvm_k1_enabled;
- /* Software state for the transmit and receive descriptors. */
- int sc_txnum; /* must be a power of two */
- struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX];
- struct wm_rxsoft sc_rxsoft[WM_NRXDESC];
-
- /* TX control data structures. */
- int sc_ntxdesc; /* must be a power of two */
- txdescs_t *sc_txdescs_u;
- bus_dmamap_t sc_txdesc_dmamap; /* control data DMA map */
- bus_dma_segment_t sc_txdesc_seg;/* control data segment */
- int sc_txdesc_rseg; /* real number of control segment */
- size_t sc_txdesc_size; /* control data size */
-#define sc_txdesc_dma sc_txdesc_dmamap->dm_segs[0].ds_addr
-#define sc_txdescs sc_txdescs_u->sctxu_txdescs
-#define sc_nq_txdescs sc_txdescs_u->sctxu_nq_txdescs
-
- /* RX control data structures. */
- wiseman_rxdesc_t *sc_rxdescs;
- bus_dmamap_t sc_rxdesc_dmamap; /* control data DMA map */
- bus_dma_segment_t sc_rxdesc_seg;/* control data segment */
- int sc_rxdesc_rseg; /* real number of control segment */
- size_t sc_rxdesc_size; /* control data size */
-#define sc_rxdesc_dma sc_rxdesc_dmamap->dm_segs[0].ds_addr
+ int sc_ntxqueues;
+ struct wm_txqueue *sc_txq;
+
+ int sc_nrxqueues;
+ struct wm_rxqueue *sc_rxq;
#ifdef WM_EVENT_COUNTERS
/* Event counters. */
@@ -374,31 +425,9 @@
struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */
#endif /* WM_EVENT_COUNTERS */
- bus_addr_t sc_tdt_reg; /* offset of TDT register */
-
- int sc_txfree; /* number of free Tx descriptors */
- int sc_txnext; /* next ready Tx descriptor */
-
- int sc_txsfree; /* number of free Tx jobs */
- int sc_txsnext; /* next free Tx job */
- int sc_txsdirty; /* dirty Tx jobs */
-
- /* These 5 variables are used only on the 82547. */
- int sc_txfifo_size; /* Tx FIFO size */
- int sc_txfifo_head; /* current head of FIFO */
- uint32_t sc_txfifo_addr; /* internal address of start of FIFO */
- int sc_txfifo_stall; /* Tx FIFO is stalled */
+ /* This variable are used only on the 82547. */
callout_t sc_txfifo_ch; /* Tx FIFO stall work-around timer */
- bus_addr_t sc_rdt_reg; /* offset of RDT register */
-
- int sc_rxptr; /* next ready Rx descriptor/queue ent */
- int sc_rxdiscard;
- int sc_rxlen;
- struct mbuf *sc_rxhead;
- struct mbuf *sc_rxtail;
- struct mbuf **sc_rxtailp;
-
uint32_t sc_ctrl; /* prototype CTRL register */
#if 0
uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */
@@ -440,17 +469,17 @@
#define CALLOUT_FLAGS 0
#endif
-#define WM_RXCHAIN_RESET(sc) \
+#define WM_RXCHAIN_RESET(rxq) \
do { \
- (sc)->sc_rxtailp = &(sc)->sc_rxhead; \
- *(sc)->sc_rxtailp = NULL; \
- (sc)->sc_rxlen = 0; \
+ (rxq)->rxq_tailp = &(rxq)->rxq_head; \
+ *(rxq)->rxq_tailp = NULL; \
+ (rxq)->rxq_len = 0; \
} while (/*CONSTCOND*/0)
-#define WM_RXCHAIN_LINK(sc, m) \
+#define WM_RXCHAIN_LINK(rxq, m) \
do { \
- *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \
- (sc)->sc_rxtailp = &(m)->m_next; \
+ *(rxq)->rxq_tailp = (rxq)->rxq_tail = (m); \
+ (rxq)->rxq_tailp = &(m)->m_next; \
} while (/*CONSTCOND*/0)
#ifdef WM_EVENT_COUNTERS
@@ -478,18 +507,18 @@
#define ICH8_FLASH_WRITE16(sc, reg, data) \
bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data))
-#define WM_CDTXADDR(sc, x) ((sc)->sc_txdesc_dma + WM_CDTXOFF((x)))
-#define WM_CDRXADDR(sc, x) ((sc)->sc_rxdesc_dma + WM_CDRXOFF((x)))
-
-#define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU)
-#define WM_CDTXADDR_HI(sc, x) \
+#define WM_CDTXADDR(txq, x) ((txq)->txq_desc_dma + WM_CDTXOFF((x)))
+#define WM_CDRXADDR(rxq, x) ((rxq)->rxq_desc_dma + WM_CDRXOFF((x)))
+
+#define WM_CDTXADDR_LO(txq, x) (WM_CDTXADDR((txq), (x)) & 0xffffffffU)
+#define WM_CDTXADDR_HI(txq, x) \
(sizeof(bus_addr_t) == 8 ? \
- (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0)
-
-#define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU)
-#define WM_CDRXADDR_HI(sc, x) \
+ (uint64_t)WM_CDTXADDR((txq), (x)) >> 32 : 0)
+
+#define WM_CDRXADDR_LO(rxq, x) (WM_CDRXADDR((rxq), (x)) & 0xffffffffU)
+#define WM_CDRXADDR_HI(rxq, x) \
(sizeof(bus_addr_t) == 8 ? \
- (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0)
+ (uint64_t)WM_CDRXADDR((rxq), (x)) >> 32 : 0)
/*
* Register read/write functions.
@@ -1337,34 +1366,37 @@
static inline void
wm_cdtxsync(struct wm_softc *sc, int start, int num, int ops)
{
+ struct wm_txqueue *txq = sc->sc_txq;
/* If it will wrap around, sync to the end of the ring. */
- if ((start + num) > WM_NTXDESC(sc)) {
- bus_dmamap_sync(sc->sc_dmat, sc->sc_txdesc_dmamap,
+ if ((start + num) > WM_NTXDESC(txq)) {
+ bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap,
WM_CDTXOFF(start), sizeof(wiseman_txdesc_t) *
- (WM_NTXDESC(sc) - start), ops);
- num -= (WM_NTXDESC(sc) - start);
+ (WM_NTXDESC(txq) - start), ops);
+ num -= (WM_NTXDESC(txq) - start);
start = 0;
}
/* Now sync whatever is left. */
- bus_dmamap_sync(sc->sc_dmat, sc->sc_txdesc_dmamap,
+ bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap,
WM_CDTXOFF(start), sizeof(wiseman_txdesc_t) * num, ops);
}
static inline void
wm_cdrxsync(struct wm_softc *sc, int start, int ops)
{
-
- bus_dmamap_sync(sc->sc_dmat, sc->sc_rxdesc_dmamap,
+ struct wm_rxqueue *rxq = sc->sc_rxq;
+
+ bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_dmamap,
WM_CDRXOFF(start), sizeof(wiseman_rxdesc_t), ops);
}
static inline void
wm_init_rxdesc(struct wm_softc *sc, int start)
{
- struct wm_rxsoft *rxs = &sc->sc_rxsoft[start];
- wiseman_rxdesc_t *rxd = &sc->sc_rxdescs[start];
+ struct wm_rxqueue *rxq = sc->sc_rxq;
+ struct wm_rxsoft *rxs = &rxq->rxq_soft[start];
+ wiseman_rxdesc_t *rxd = &rxq->rxq_descs[start];
struct mbuf *m = rxs->rxs_mbuf;
/*
@@ -1392,7 +1424,7 @@
rxd->wrx_special = 0;
wm_cdrxsync(sc, start, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
- CSR_WRITE(sc, sc->sc_rdt_reg, start);
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