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[src/trunk]: src/sys/arch Split out USB PHY support out of the ehci glue and ...
details: https://anonhg.NetBSD.org/src/rev/ecea5c1f3691
branches: trunk
changeset: 341153:ecea5c1f3691
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Wed Oct 21 20:02:12 2015 +0000
description:
Split out USB PHY support out of the ehci glue and into a separate driver.
diffstat:
sys/arch/arm/nvidia/files.tegra | 7 +-
sys/arch/arm/nvidia/tegra_ehci.c | 210 +------------------------
sys/arch/arm/nvidia/tegra_ehcireg.h | 127 ---------------
sys/arch/arm/nvidia/tegra_io.c | 8 +-
sys/arch/arm/nvidia/tegra_usbphy.c | 283 ++++++++++++++++++++++++++++++++++
sys/arch/arm/nvidia/tegra_usbreg.h | 127 +++++++++++++++
sys/arch/evbarm/conf/JETSONTK1 | 4 +-
sys/arch/evbarm/tegra/tegra_machdep.c | 6 +-
8 files changed, 431 insertions(+), 341 deletions(-)
diffs (truncated from 915 to 300 lines):
diff -r 1a7d7fd8d864 -r ecea5c1f3691 sys/arch/arm/nvidia/files.tegra
--- a/sys/arch/arm/nvidia/files.tegra Wed Oct 21 15:47:19 2015 +0000
+++ b/sys/arch/arm/nvidia/files.tegra Wed Oct 21 20:02:12 2015 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.tegra,v 1.18 2015/10/19 21:18:36 jmcneill Exp $
+# $NetBSD: files.tegra,v 1.19 2015/10/21 20:02:12 jmcneill Exp $
#
# Configuration info for NVIDIA Tegra ARM Peripherals
#
@@ -71,6 +71,11 @@
attach tegrartc at tegraio with tegra_rtc
file arch/arm/nvidia/tegra_rtc.c tegra_rtc
+# USB PHY
+device tegrausbphy
+attach tegrausbphy at tegraio with tegra_usbphy
+file arch/arm/nvidia/tegra_usbphy.c tegra_usbphy
+
# USB 2.0
attach ehci at tegraio with tegra_ehci
file arch/arm/nvidia/tegra_ehci.c tegra_ehci
diff -r 1a7d7fd8d864 -r ecea5c1f3691 sys/arch/arm/nvidia/tegra_ehci.c
--- a/sys/arch/arm/nvidia/tegra_ehci.c Wed Oct 21 15:47:19 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_ehci.c Wed Oct 21 20:02:12 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_ehci.c,v 1.8 2015/10/21 10:43:09 jmcneill Exp $ */
+/* $NetBSD: tegra_ehci.c,v 1.9 2015/10/21 20:02:12 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
#include "locators.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_ehci.c,v 1.8 2015/10/21 10:43:09 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_ehci.c,v 1.9 2015/10/21 20:02:12 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -46,7 +46,7 @@
#include <dev/usb/ehcivar.h>
#include <arm/nvidia/tegra_var.h>
-#include <arm/nvidia/tegra_ehcireg.h>
+#include <arm/nvidia/tegra_usbreg.h>
#define TEGRA_EHCI_REG_OFFSET 0x100
@@ -61,22 +61,8 @@
bus_space_handle_t sc_bsh;
void *sc_ih;
u_int sc_port;
-
- struct tegra_gpio_pin *sc_pin_vbus;
- uint8_t sc_hssync_start_delay;
- uint8_t sc_idle_wait_delay;
- uint8_t sc_elastic_limit;
- uint8_t sc_term_range_adj;
- uint8_t sc_xcvr_setup;
- uint8_t sc_xcvr_lsfslew;
- uint8_t sc_xcvr_lsrslew;
- uint8_t sc_hssquelch_level;
- uint8_t sc_hsdiscon_level;
- uint8_t sc_xcvr_hsslew;
};
-static int tegra_ehci_parse_properties(struct tegra_ehci_softc *);
-static void tegra_ehci_utmip_init(struct tegra_ehci_softc *);
static int tegra_ehci_port_status(struct ehci_softc *sc, uint32_t v,
int i);
@@ -96,8 +82,6 @@
struct tegra_ehci_softc * const sc = device_private(self);
struct tegraio_attach_args * const tio = aux;
const struct tegra_locators * const loc = &tio->tio_loc;
- prop_dictionary_t prop = device_properties(self);
- const char *pin;
int error;
sc->sc_bst = tio->tio_bst;
@@ -124,27 +108,6 @@
aprint_naive("\n");
aprint_normal(": USB%d\n", loc->loc_port + 1);
- if (tegra_ehci_parse_properties(sc) != 0)
- return;
-
- tegra_car_periph_usb_enable(sc->sc_port);
- delay(2);
-
- tegra_ehci_utmip_init(sc);
-
- if (prop_dictionary_get_cstring_nocopy(prop, "vbus-gpio", &pin)) {
- const uint32_t v = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
- TEGRA_EHCI_PHY_VBUS_SENSORS_REG);
- if ((v & TEGRA_EHCI_PHY_VBUS_SENSORS_A_VBUS_VLD_STS) == 0) {
- sc->sc_pin_vbus = tegra_gpio_acquire(pin,
- GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN);
- if (sc->sc_pin_vbus)
- tegra_gpio_write(sc->sc_pin_vbus, 1);
- } else {
- aprint_normal_dev(self, "VBUS input active\n");
- }
- }
-
sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
sc->sc_ih = intr_establish(loc->loc_intr, IPL_USB, IST_LEVEL,
@@ -165,33 +128,6 @@
sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
}
-static int
-tegra_ehci_parse_properties(struct tegra_ehci_softc *sc)
-{
-#define PROPGET(k, v) \
- if (prop_dictionary_get_uint8(prop, (k), (v)) == false) { \
- aprint_error_dev(sc->sc.sc_dev, \
- "missing property '%s'\n", (k)); \
- return EIO; \
- }
-
- prop_dictionary_t prop = device_properties(sc->sc.sc_dev);
-
- PROPGET("nvidia,hssync-start-delay", &sc->sc_hssync_start_delay);
- PROPGET("nvidia,idle-wait-delay", &sc->sc_idle_wait_delay);
- PROPGET("nvidia,elastic-limit", &sc->sc_elastic_limit);
- PROPGET("nvidia,term-range-adj", &sc->sc_term_range_adj);
- PROPGET("nvidia,xcvr-setup", &sc->sc_xcvr_setup);
- PROPGET("nvidia,xcvr-lsfslew", &sc->sc_xcvr_lsfslew);
- PROPGET("nvidia,xcvr-lsrslew", &sc->sc_xcvr_lsrslew);
- PROPGET("nvidia,hssquelch-level", &sc->sc_hssquelch_level);
- PROPGET("nvidia,hsdiscon-level", &sc->sc_hsdiscon_level);
- PROPGET("nvidia,xcvr-hsslew", &sc->sc_xcvr_hsslew);
-
- return 0;
-#undef PROPGET
-}
-
static void
tegra_ehci_init(struct ehci_softc *esc)
{
@@ -223,146 +159,6 @@
__SHIFTIN(0x10, TEGRA_EHCI_TXFILLTUNING_TXFIFOTHRES));
}
-static void
-tegra_ehci_utmip_init(struct tegra_ehci_softc *sc)
-{
- bus_space_tag_t bst = sc->sc_bst;
- bus_space_handle_t bsh = sc->sc_bsh;
- int retry;
-
- /* Put UTMIP PHY into reset before programming UTMIP config registers */
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG,
- TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET, 0);
-
- /* Enable UTMIP PHY mode */
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG,
- TEGRA_EHCI_SUSP_CTRL_UTMIP_PHY_ENB, 0);
-
- /* Stop crystal clock */
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG,
- 0, TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN);
- delay(1);
-
- /* Clear session status */
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_PHY_VBUS_SENSORS_REG,
- 0,
- TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_VALUE |
- TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_EN);
-
- /* PLL configuration */
- tegra_car_utmip_init();
-
- /* Transceiver configuration */
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG,
- __SHIFTIN(4, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP) |
- __SHIFTIN(3, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB) |
- __SHIFTIN(sc->sc_xcvr_hsslew,
- TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB),
- TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP |
- TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB |
- TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB);
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG,
- __SHIFTIN(sc->sc_term_range_adj,
- TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ),
- TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ);
-
- if (sc->sc_port == 0) {
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG0_REG,
- TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL_MSB |
- __SHIFTIN(sc->sc_hsdiscon_level,
- TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL),
- TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL);
- }
-
- /* Misc config */
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG0_REG,
- 0,
- TEGRA_EHCI_UTMIP_MISC_CFG0_SUSPEND_EXIT_ON_EDGE);
-
- /* BIAS cell power down lag */
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG,
- __SHIFTIN(5, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT),
- TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT);
-
- /* Debounce config */
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_REG,
- __SHIFTIN(0x7530, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A),
- TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A);
-
- /* Transmit signal preamble config */
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_TX_CFG0_REG,
- TEGRA_EHCI_UTMIP_TX_CFG0_FS_PREAMBLE_J, 0);
-
- /* Power-down battery charger circuit */
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_REG,
- TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_PD_CHRG, 0);
-
- /* Select low speed bias method */
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG,
- 0, TEGRA_EHCI_UTMIP_XCVR_CFG0_LSBIAS_SEL);
-
- /* High speed receive config */
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG0_REG,
- __SHIFTIN(sc->sc_idle_wait_delay,
- TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT) |
- __SHIFTIN(sc->sc_elastic_limit,
- TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT),
- TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT |
- TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT);
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG1_REG,
- __SHIFTIN(sc->sc_hssync_start_delay,
- TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY),
- TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY);
-
- /* Start crystal clock */
- delay(1);
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG,
- TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN, 0);
-
- /* Clear port PLL powerdown status */
- tegra_car_utmip_enable(sc->sc_port);
-
- /* Bring UTMIP PHY out of reset */
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG,
- 0, TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET);
- for (retry = 100000; retry > 0; retry--) {
- const uint32_t susp = bus_space_read_4(bst, bsh,
- TEGRA_EHCI_SUSP_CTRL_REG);
- if (susp & TEGRA_EHCI_SUSP_CTRL_PHY_CLK_VALID)
- break;
- delay(1);
- }
- if (retry == 0) {
- aprint_error_dev(sc->sc.sc_dev, "PHY clock is not valid\n");
- return;
- }
-
- /* Disable ICUSB transceiver */
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_ICUSB_CTRL_REG,
- 0,
- TEGRA_EHCI_ICUSB_CTRL_ENB1);
-
- /* Power up UTMPI transceiver */
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG,
- 0,
- TEGRA_EHCI_UTMIP_XCVR_CFG0_PD_POWERDOWN |
- TEGRA_EHCI_UTMIP_XCVR_CFG0_PD2_POWERDOWN |
- TEGRA_EHCI_UTMIP_XCVR_CFG0_PDZI_POWERDOWN);
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG,
- 0,
- TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDISC_POWERDOWN |
- TEGRA_EHCI_UTMIP_XCVR_CFG1_PDCHRP_POWERDOWN |
- TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDR_POWERDOWN);
-
- if (sc->sc_port == 0) {
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG0_REG,
- 0, TEGRA_EHCI_UTMIP_BIAS_CFG0_BIASPD);
- delay(25);
- tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG,
- 0, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_POWERDOWN);
- }
-}
-
static int
tegra_ehci_port_status(struct ehci_softc *ehci_sc, uint32_t v, int i)
{
diff -r 1a7d7fd8d864 -r ecea5c1f3691 sys/arch/arm/nvidia/tegra_ehcireg.h
--- a/sys/arch/arm/nvidia/tegra_ehcireg.h Wed Oct 21 15:47:19 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,127 +0,0 @@
-/* $NetBSD: tegra_ehcireg.h,v 1.2 2015/05/18 09:56:43 skrll Exp $ */
-
-/*-
- * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
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