[src/trunk]: src/sys/arch/amd64/include KNF so it appears aligned on NXR, and...

[maxv <maxv%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/7df38736ff42
branches:  trunk
changeset: 345246:7df38736ff42
user:      maxv <maxv%NetBSD.org@localhost>
date:      Sat May 14 12:48:31 2016 +0000

description:
KNF so it appears aligned on NXR, and fix a comment.

diffstat:

 sys/arch/amd64/include/pmap.h |  21 ++++++++++-----------
 1 files changed, 10 insertions(+), 11 deletions(-)

diffs (48 lines):

diff -r 5916a73eca99 -r 7df38736ff42 sys/arch/amd64/include/pmap.h
--- a/sys/arch/amd64/include/pmap.h     Sat May 14 10:52:29 2016 +0000
+++ b/sys/arch/amd64/include/pmap.h     Sat May 14 12:48:31 2016 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.h,v 1.35 2015/01/09 01:08:49 riastradh Exp $      */
+/*     $NetBSD: pmap.h,v 1.36 2016/05/14 12:48:31 maxv Exp $   */
 
 /*
  * Copyright (c) 1997 Charles D. Cranor and Washington University.
@@ -161,21 +161,20 @@
 #define PDIR_SLOT_PTE  L4_SLOT_PTE
 
 /*
- * the following defines give the virtual addresses of various MMU
+ * The following defines give the virtual addresses of various MMU
  * data structures:
  * PTE_BASE: the base VA of the linear PTE mappings
- * PTD_BASE: the base VA of the recursive mapping of the PTD
+ * PDP_BASE: the base VA of the recursive mapping of the PTD
  * PDP_PDE: the VA of the PDE that points back to the PDP
- *
  */
 
-#define PTE_BASE  ((pt_entry_t *) (L4_SLOT_PTE * NBPD_L4))
-#define KERN_BASE  ((pt_entry_t *) (L4_SLOT_KERN * NBPD_L4))
+#define PTE_BASE       ((pt_entry_t *)(L4_SLOT_PTE * NBPD_L4))
+#define KERN_BASE      ((pt_entry_t *)(L4_SLOT_KERN * NBPD_L4))
 
-#define L1_BASE                PTE_BASE
-#define L2_BASE ((pd_entry_t *)((char *)L1_BASE + L4_SLOT_PTE * NBPD_L3))
-#define L3_BASE ((pd_entry_t *)((char *)L2_BASE + L4_SLOT_PTE * NBPD_L2))
-#define L4_BASE ((pd_entry_t *)((char *)L3_BASE + L4_SLOT_PTE * NBPD_L1))
+#define L1_BASE        PTE_BASE
+#define L2_BASE        ((pd_entry_t *)((char *)L1_BASE + L4_SLOT_PTE * NBPD_L3))
+#define L3_BASE        ((pd_entry_t *)((char *)L2_BASE + L4_SLOT_PTE * NBPD_L2))
+#define L4_BASE        ((pd_entry_t *)((char *)L3_BASE + L4_SLOT_PTE * NBPD_L1))
 
 #define PDP_PDE                (L4_BASE + PDIR_SLOT_PTE)
 
@@ -307,7 +306,7 @@
 
 static __inline void
 pmap_pte_clearbits(volatile pt_entry_t *pte, pt_entry_t bits)
-{      
+{
        mutex_enter(&pte_lock);
        xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(pte)),
            (*pte) & ~bits);