[src/trunk]: src/sys/arch/sparc64/sparc64 sun4v: Ensure that the W (Write) bi...

[palle <palle%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/459a93305be7
branches:  trunk
changeset: 337179:459a93305be7
user:      palle <palle%NetBSD.org@localhost>
date:      Sun Apr 05 20:26:47 2015 +0000

description:
sun4v: Ensure that the W (Write) bit is not present in the TTEs unless for the data mapping. This way the permanent mappings for the primary cpu done by ofwboot are the same as the permanent mappings 
for the secondary cpus done by the kernel. This should fix an issue when booting the kernel on a T2 based system (T5120).

diffstat:

 sys/arch/sparc64/sparc64/pmap.c |  21 ++++++++++++++++-----
 1 files changed, 16 insertions(+), 5 deletions(-)

diffs (47 lines):

diff -r 641ec4029ffa -r 459a93305be7 sys/arch/sparc64/sparc64/pmap.c
--- a/sys/arch/sparc64/sparc64/pmap.c   Sun Apr 05 17:05:45 2015 +0000
+++ b/sys/arch/sparc64/sparc64/pmap.c   Sun Apr 05 20:26:47 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.c,v 1.292 2014/11/04 18:11:42 palle Exp $ */
+/*     $NetBSD: pmap.c,v 1.293 2015/04/05 20:26:47 palle Exp $ */
 /*
  *
  * Copyright (C) 1996-1999 Eduardo Horvath.
@@ -26,7 +26,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.292 2014/11/04 18:11:42 palle Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.293 2015/04/05 20:26:47 palle Exp $");
 
 #undef NO_VCACHE /* Don't forget the locked TLB in dostart */
 #define        HWREF
@@ -535,14 +535,25 @@
                                PGSZ_4M,                /* sz */
                                kernel_tlbs[i].te_pa,   /* pa */
                                1, /* priv */
-                               1, /* write */
+                               0, /* write */
                                1, /* cache */
                                1, /* aliased */
                                1, /* valid */
                                0 /* ie */);
                tp[i].data |= TLB_L | TLB_CV;
-               if (CPU_ISSUN4V)
-                       tp[i].data |= SUN4V_TLB_X;
+
+               /*
+                * Assuming that the last tlb slot entry is the only data slot.
+                *
+                * If more than one data slot is required on day, perhaps
+                * the bootinfo structure shared between ofwboot and the kernel
+                * should be expanded to include the number of data slots.
+                */
+               if (i == kernel_tlb_slots-1)
+                       tp[i].data |= TLB_W;
+               else
+                       if (CPU_ISSUN4V)
+                               tp[i].data |= SUN4V_TLB_X;
                        
                DPRINTF(PDB_BOOT1, ("xtlb[%d]: Tag: %" PRIx64 " Data: %"
                                PRIx64 "\n", i, tp[i].tag, tp[i].data));