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[src/trunk]: src/sys/arch/riscv/include Switch to new ABI (return values now ...
details: https://anonhg.NetBSD.org/src/rev/c7abb7748b6a
branches: trunk
changeset: 336916:c7abb7748b6a
user: matt <matt%NetBSD.org@localhost>
date: Fri Mar 27 06:57:21 2015 +0000
description:
Switch to new ABI (return values now in a0/a1; v0/v1 are no more)
diffstat:
sys/arch/riscv/include/asm.h | 6 +-
sys/arch/riscv/include/elf_machdep.h | 94 +++++++++++++++++------------------
sys/arch/riscv/include/mcontext.h | 12 ++--
sys/arch/riscv/include/reg.h | 87 ++++++++++++++++++--------------
sys/arch/riscv/include/setjmp.h | 66 +++++++++++-------------
5 files changed, 134 insertions(+), 131 deletions(-)
diffs (truncated from 354 to 300 lines):
diff -r 39c649ddc7a9 -r c7abb7748b6a sys/arch/riscv/include/asm.h
--- a/sys/arch/riscv/include/asm.h Fri Mar 27 06:44:28 2015 +0000
+++ b/sys/arch/riscv/include/asm.h Fri Mar 27 06:57:21 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: asm.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */
+/* $NetBSD: asm.h,v 1.2 2015/03/27 06:57:21 matt Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -119,9 +119,9 @@
#define RCSID(name) __RCSID(name)
#if defined(_LP64)
-#define SZREG 4
+#define SZREG 8
#else
-#define SZREG 8
+#define SZREG 4
#endif
#define ALSK 15 /* stack alignment */
diff -r 39c649ddc7a9 -r c7abb7748b6a sys/arch/riscv/include/elf_machdep.h
--- a/sys/arch/riscv/include/elf_machdep.h Fri Mar 27 06:44:28 2015 +0000
+++ b/sys/arch/riscv/include/elf_machdep.h Fri Mar 27 06:57:21 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: elf_machdep.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */
+/* $NetBSD: elf_machdep.h,v 1.2 2015/03/27 06:57:21 matt Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -56,59 +56,55 @@
/* Processor specific relocation types */
#define R_RISCV_NONE 0
-#define R_RISCV_32 2 // A
-#define R_RISCV_REL32 3 // A & 0xffff
-#define R_RISCV_JAL 4 // A & 0xff
-#define R_RISCV_HI20 5 // A & 0xffff
-#define R_RISCV_LO12_I 6 // (A >> 16) & 0xffff
-#define R_RISCV_LO12_S 7 // (S + A - P) >> 2
-#define R_RISCV_PCREL_LO12_I 8
-#define R_RISCV_PCREL_LO12_S 9
-#define R_RISCV_BRANCH 10 // (A - P) & 0xffff
-#define R_RISCV_CALL 11 // (A - P) & 0xff
-#define R_RISCV_PCREL_HI20 12
-#define R_RISCV_CALL_PLT 13
-#define R_RISCV_64 18
-#define R_RISCV_GOT_HI20 22
-#define R_RISCV_GOT_LO12 23
-#define R_RISCV_COPY 24
-#define R_RISCV_JMP_SLOT 25
-/* TLS relocations. */
-#define R_RISCV_TLS_IE_HI20 29
-#define R_RISCV_TLS_IE_LO12 30
-#define R_RISCV_TLS_IE_ADD 31
-#define R_RISCV_TLS_IE_LO12_I 32
-#define R_RISCV_TLS_IE_LO12_S 33
-#define R_RISCV_TPREL_HI20 34
-#define R_RISCV_TLREL_LO12_I 35
-#define R_RISCV_TLREL_LO12_S 36
-#define R_RISCV_TLREL_ADD 37
+#define R_RISCV_32 1 // A
+#define R_RISCV_64 2
+#define R_RISCV_RELATIVE 3
+#define R_RISCV_COPY 4
+#define R_RISCV_JMP_SLOT 5
+#define R_RISCV_TLS_DTPMOD32 6
+#define R_RISCV_TLS_DTPREL32 7
+#define R_RISCV_TLS_DTPMOD64 8
+#define R_RISCV_TLS_DTPREL64 9
+#define R_RISCV_TLS_TPREL32 10
+#define R_RISCV_TLS_DTPREL64 11
-#define R_RISCV_TLS_DTPMOD32 38
-#define R_RISCV_TLS_DTPREL32 39
-#define R_RISCV_TLS_DTPMOD64 40
-#define R_RISCV_TLS_DTPREL64 41
-#define R_RISCV_TLS_DTPREL_HI16 44
-#define R_RISCV_TLS_DTPREL_LO16 45
-#define R_RISCV_TLS_PCREL_LO12 50
-#define R_RISCV_TLS_GOT_HI20 51
-#define R_RISCV_TLS_GOT_LO20 52
-#define R_RISCV_TLS_GD_HI20 53
-#define R_RISCV_TLS_GD_LO20 54
+/* The rest are not used by the dynamic linker */
+#define R_RISCV_BRANCH 16 // (A - P) & 0xffff
+#define R_RISCV_JAL 17 // A & 0xff
+#define R_RISCV_CALL 18 // (A - P) & 0xff
+#define R_RISCV_CALL_PLT 19
+#define R_RISCV_GOT_HI20 20
+#define R_RISCV_TLS_GOT_HI20 21
+#define R_RISCV_TLS_GD_HI20 22
+#define R_RISCV_PCREL_HI20 23
+#define R_RISCV_PCREL_LO12_I 24
+#define R_RISCV_PCREL_LO12_S 25
+#define R_RISCV_HI20 26 // A & 0xffff
+#define R_RISCV_LO12_I 27 // (A >> 16) & 0xffff
+#define R_RISCV_LO12_S 28 // (S + A - P) >> 2
+#define R_RISCV_TPREL_HI20 29
+#define R_RISCV_TLREL_LO12_I 30
+#define R_RISCV_TLREL_LO12_S 31
+#define R_RISCV_TLREL_ADD 32
+#define R_RISCV_ADD8 33
+#define R_RISCV_ADD16 34
+#define R_RISCV_ADD32 35
+#define R_RISCV_ADD64 36
+#define R_RISCV_SUB8 37
+#define R_RISCV_SUB16 38
+#define R_RISCV_SUB32 39
+#define R_RISCV_SUB64 40
+#define R_RISCV_GNU_VTINHERIT 41 // A & 0xffff
+#define R_RISCV_GNU_VTENTRY 42
+#define R_RISCV_ALIGN 43
-#define R_RISCV_GLOB_DAT 57
-#define R_RISCV_ADD32 58
-#define R_RISCV_SUB32 59
-#define R_RISCV_ADD64 60
-#define R_RISCV_SUB64 61
#define R_TYPE(name) R_RISCV_ ## name
+#if ELFSIZE == 32
+#define R_TLS_TYPE(name) R_RISCV_ ## name ## 32
+#else
#define R_TLS_TYPE(name) R_RISCV_ ## name ## 64
-
-#define DT_RISCV_LOCAL_GOTNO (DT_LOPROC + 0)
-#define DT_RISCV_SYMTABNO (DT_LOPROC + 1)
-#define DT_RISCV_GOTSYM (DT_LOPROC + 2)
-#define DT_RISCV_PLTGOT (DT_LOPROC + 3)
+#endif
#ifdef _KERNEL
#ifdef ELFSIZE
diff -r 39c649ddc7a9 -r c7abb7748b6a sys/arch/riscv/include/mcontext.h
--- a/sys/arch/riscv/include/mcontext.h Fri Mar 27 06:44:28 2015 +0000
+++ b/sys/arch/riscv/include/mcontext.h Fri Mar 27 06:57:21 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mcontext.h,v 1.2 2014/10/24 01:08:07 dennis Exp $ */
+/* $NetBSD: mcontext.h,v 1.3 2015/03/27 06:57:21 matt Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -88,11 +88,11 @@
#define _REG_PC 31
#define _REG_RA _REG_X1
-#define _REG_SP _REG_X14
-#define _REG_TP _REG_X15
-#define _REG_RV _REG_X16
-#define _REG_A0 _REG_X18
-#define _REG_GP _REG_X31
+#define _REG_SP _REG_X2
+#define _REG_GP _REG_X3
+#define _REG_TP _REG_X4
+#define _REG_RV _REG_X10
+#define _REG_A0 _REG_X10
#define _REG_F0 0
#define _REG_FPCSR 32
diff -r 39c649ddc7a9 -r c7abb7748b6a sys/arch/riscv/include/reg.h
--- a/sys/arch/riscv/include/reg.h Fri Mar 27 06:44:28 2015 +0000
+++ b/sys/arch/riscv/include/reg.h Fri Mar 27 06:57:21 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: reg.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */
+/* $NetBSD: reg.h,v 1.2 2015/03/27 06:57:21 matt Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -34,14 +34,17 @@
// x0 = 0
// x1 = ra (return address)
-// x2 = s0/fp (frame pointer)
-// x3-r13 = saved registers
-// x14 = sp (stack pointer)
-// x15 = tp (thread pointer)
-// x16-x17 = v0/v1 (return value)
-// x18-x25 = a0-a7 (arguements)
+// x2 = sp (stack pointer)
+// x3 = gp (global pointer)
+// x4 = tp (thread pointer)
+// x5-x7 = t0-t2 (temporary)
+// x8 = s0/fp (saved register / frame pointer)
+// x9 = s1 (saved register)
+// x10-x11 = a0-a1 (arguments/return values)
+// x12-x17 = a2-a7 (arguments)
+// x18-r27 = s2-s11 (saved registers)
+// x28-x31 = t3-r6 (temporaries)
// x26-x30 = t0-t4 (temporary)
-// x31 = global pointer
struct reg { // synced with register_t in <riscv/types.h>
#ifdef _LP64
@@ -62,36 +65,44 @@
#define _XREG(n) ((n)-1)
#define _X_RA _XREG(1)
-#define _X_S0 _XREG(2)
-#define _X_S1 _XREG(3)
-#define _X_S2 _XREG(4)
-#define _X_S3 _XREG(5)
-#define _X_S4 _XREG(6)
-#define _X_S5 _XREG(7)
-#define _X_S6 _XREG(8)
-#define _X_S7 _XREG(9)
-#define _X_S8 _XREG(10)
-#define _X_S9 _XREG(11)
-#define _X_S10 _XREG(12)
-#define _X_S11 _XREG(13)
-#define _X_SP _XREG(14)
-#define _X_TP _XREG(15)
-#define _X_V0 _XREG(16)
-#define _X_V1 _XREG(17)
-#define _X_A0 _XREG(18)
-#define _X_A1 _XREG(19)
-#define _X_A2 _XREG(20)
-#define _X_A3 _XREG(21)
-#define _X_A4 _XREG(22)
-#define _X_A5 _XREG(23)
-#define _X_A6 _XREG(24)
-#define _X_A7 _XREG(25)
-#define _X_T0 _XREG(26)
-#define _X_T1 _XREG(27)
-#define _X_T2 _XREG(28)
-#define _X_T3 _XREG(29)
-#define _X_T4 _XREG(30)
-#define _X_GP _XREG(31)
+#define _X_SP _XREG(2)
+#define _X_GP _XREG(3)
+#define _X_TP _XREG(4)
+#define _X_T0 _XREG(5)
+#define _X_T1 _XREG(6)
+#define _X_T2 _XREG(7)
+#define _X_S0 _XREG(8)
+#define _X_S1 _XREG(9)
+#define _X_A0 _XREG(10)
+#define _X_A1 _XREG(11)
+#define _X_A2 _XREG(12)
+#define _X_A3 _XREG(13)
+#define _X_A4 _XREG(14)
+#define _X_A5 _XREG(15)
+#define _X_A6 _XREG(16)
+#define _X_A7 _XREG(17)
+#define _X_S2 _XREG(18)
+#define _X_S3 _XREG(19)
+#define _X_S4 _XREG(20)
+#define _X_S5 _XREG(21)
+#define _X_S6 _XREG(22)
+#define _X_S7 _XREG(23)
+#define _X_S8 _XREG(24)
+#define _X_S9 _XREG(25)
+#define _X_S10 _XREG(26)
+#define _X_S11 _XREG(27)
+#define _X_T3 _XREG(28)
+#define _X_T4 _XREG(29)
+#define _X_T5 _XREG(30)
+#define _X_T6 _XREG(31)
+
+// f0-f7 = ft0-ft7 (FP temporaries)
+// following layout is similar to integer registers above
+// f8-f9 = fs0-fs1 (FP saved registers)
+// f10-f11 = fa0-fa1 (FP arguments/return values)
+// f12-f17 = fa2-fa7 (FP arguments)
+// f18-f27 = fs2-fa11 (FP saved registers)
+// f28-f31 = ft8-ft11 (FP temporaries)
/*
* This fragment is common to <riscv/mcontext.h> and <riscv/reg.h>
diff -r 39c649ddc7a9 -r c7abb7748b6a sys/arch/riscv/include/setjmp.h
--- a/sys/arch/riscv/include/setjmp.h Fri Mar 27 06:44:28 2015 +0000
+++ b/sys/arch/riscv/include/setjmp.h Fri Mar 27 06:57:21 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: setjmp.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */
+/* $NetBSD: setjmp.h,v 1.2 2015/03/27 06:57:21 matt Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -29,45 +29,41 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
- /* magic + 16 reg + 1 fcsr + 16 fp + 4 sigmask */
-#define _JBLEN (_JB_SIGMASK + 4)
+ /* magic + 16 reg + 1 fcsr + 12 fp + 4 sigmask + 8 spare */
+#define _JBLEN (_JB_SIGMASK + 4 + 8)
#define _JB_MAGIC 0
#define _JB_RA 1
-#define _JB_S0 2
-#define _JB_S1 3
-#define _JB_S2 4
-#define _JB_S3 5
-#define _JB_S4 6
-#define _JB_S5 7
-#define _JB_S6 8
-#define _JB_S7 9
-#define _JB_S8 10
-#define _JB_S9 11
-#define _JB_S10 12
-#define _JB_S11 13
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