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[src/trunk]: src/external/gpl3/gcc/dist/gcc Update gcc to use new ABI for RISCV
details: https://anonhg.NetBSD.org/src/rev/a77a09434037
branches: trunk
changeset: 336903:a77a09434037
user: matt <matt%NetBSD.org@localhost>
date: Fri Mar 27 01:51:34 2015 +0000
description:
Update gcc to use new ABI for RISCV
diffstat:
external/gpl3/gcc/dist/gcc/common/config/riscv/riscv-common.c | 81 +-
external/gpl3/gcc/dist/gcc/config/riscv/constraints.md | 7 +-
external/gpl3/gcc/dist/gcc/config/riscv/crti.asm | 42 -
external/gpl3/gcc/dist/gcc/config/riscv/crtn.asm | 38 -
external/gpl3/gcc/dist/gcc/config/riscv/default-32.h | 22 +
external/gpl3/gcc/dist/gcc/config/riscv/div.S | 121 -
external/gpl3/gcc/dist/gcc/config/riscv/elf.h | 2 +-
external/gpl3/gcc/dist/gcc/config/riscv/linux.h | 2 +-
external/gpl3/gcc/dist/gcc/config/riscv/linux64.h | 3 +-
external/gpl3/gcc/dist/gcc/config/riscv/opcode-riscv.h | 5 +-
external/gpl3/gcc/dist/gcc/config/riscv/peephole.md | 48 +-
external/gpl3/gcc/dist/gcc/config/riscv/riscv-fp.c | 178 -
external/gpl3/gcc/dist/gcc/config/riscv/riscv-opc.h | 166 +-
external/gpl3/gcc/dist/gcc/config/riscv/riscv-protos.h | 14 +-
external/gpl3/gcc/dist/gcc/config/riscv/riscv.c | 924 ++-------
external/gpl3/gcc/dist/gcc/config/riscv/riscv.h | 246 +-
external/gpl3/gcc/dist/gcc/config/riscv/riscv.md | 256 +-
external/gpl3/gcc/dist/gcc/config/riscv/riscv.opt | 18 +-
external/gpl3/gcc/dist/gcc/config/riscv/sync.md | 21 +-
external/gpl3/gcc/dist/gcc/config/riscv/t-elf | 5 +-
external/gpl3/gcc/dist/gcc/config/riscv/t-linux64 | 5 +-
21 files changed, 738 insertions(+), 1466 deletions(-)
diffs (truncated from 3515 to 300 lines):
diff -r d8a511706364 -r a77a09434037 external/gpl3/gcc/dist/gcc/common/config/riscv/riscv-common.c
--- a/external/gpl3/gcc/dist/gcc/common/config/riscv/riscv-common.c Thu Mar 26 22:20:42 2015 +0000
+++ b/external/gpl3/gcc/dist/gcc/common/config/riscv/riscv-common.c Fri Mar 27 01:51:34 2015 +0000
@@ -25,16 +25,85 @@
#include "common/common-target-def.h"
#include "opts.h"
#include "flags.h"
+#include "errors.h"
+
+/* Parse a RISC-V ISA string into an option mask. */
+
+static void
+riscv_parse_arch_string (const char *isa, int *flags)
+{
+ const char *p = isa;
+
+ if (strncmp (p, "RV32", 4) == 0)
+ *flags |= MASK_32BIT, p += 4;
+ else if (strncmp (p, "RV64", 4) == 0)
+ *flags &= ~MASK_32BIT, p += 4;
+
+ if (*p++ != 'I')
+ {
+ error ("-march=%s: ISA strings must begin with I, RV32I, or RV64I", isa);
+ return;
+ }
+
+ *flags &= ~MASK_MULDIV;
+ if (*p == 'M')
+ *flags |= MASK_MULDIV, p++;
+
+ *flags &= ~MASK_ATOMIC;
+ if (*p == 'A')
+ *flags |= MASK_ATOMIC, p++;
+
+ *flags |= MASK_SOFT_FLOAT_ABI;
+ if (*p == 'F')
+ *flags &= ~MASK_SOFT_FLOAT_ABI, p++;
+
+ if (*p == 'D')
+ {
+ p++;
+ if (!TARGET_HARD_FLOAT)
+ {
+ error ("-march=%s: the D extension requires the F extension", isa);
+ return;
+ }
+ }
+ else if (TARGET_HARD_FLOAT)
+ {
+ error ("-march=%s: single-precision-only is not yet supported", isa);
+ return;
+ }
+
+ if (*p)
+ {
+ error ("-march=%s: unsupported ISA substring %s", isa, p);
+ return;
+ }
+}
+
+static int
+riscv_flags_from_arch_string (const char *isa)
+{
+ int flags = 0;
+ riscv_parse_arch_string (isa, &flags);
+ return flags;
+}
/* Implement TARGET_HANDLE_OPTION. */
static bool
-riscv_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED,
+riscv_handle_option (struct gcc_options *opts,
struct gcc_options *opts_set ATTRIBUTE_UNUSED,
- const struct cl_decoded_option *decoded ATTRIBUTE_UNUSED,
+ const struct cl_decoded_option *decoded,
location_t loc ATTRIBUTE_UNUSED)
{
- return true;
+ switch (decoded->opt_index)
+ {
+ case OPT_march_:
+ riscv_parse_arch_string (decoded->arg, &opts->x_target_flags);
+ return true;
+
+ default:
+ return true;
+ }
}
/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
@@ -49,10 +118,10 @@
#define TARGET_OPTION_OPTIMIZATION_TABLE riscv_option_optimization_table
#undef TARGET_DEFAULT_TARGET_FLAGS
-#define TARGET_DEFAULT_TARGET_FLAGS \
- (TARGET_DEFAULT \
- | TARGET_CPU_DEFAULT \
+#define TARGET_DEFAULT_TARGET_FLAGS \
+ (riscv_flags_from_arch_string (RISCV_ARCH_STRING_DEFAULT) \
| (TARGET_64BIT_DEFAULT ? 0 : MASK_32BIT))
+
#undef TARGET_HANDLE_OPTION
#define TARGET_HANDLE_OPTION riscv_handle_option
diff -r d8a511706364 -r a77a09434037 external/gpl3/gcc/dist/gcc/config/riscv/constraints.md
--- a/external/gpl3/gcc/dist/gcc/config/riscv/constraints.md Thu Mar 26 22:20:42 2015 +0000
+++ b/external/gpl3/gcc/dist/gcc/config/riscv/constraints.md Fri Mar 27 01:51:34 2015 +0000
@@ -60,16 +60,11 @@
"@internal"
(match_operand 0 "const_arith_operand"))
-(define_memory_constraint "YR"
+(define_memory_constraint "A"
"An address that is held in a general-purpose register."
(and (match_code "mem")
(match_test "GET_CODE(XEXP(op,0)) == REG")))
-(define_memory_constraint "R"
- "An address that can be used in a non-macro load or store."
- (and (match_code "mem")
- (match_test "riscv_address_insns (XEXP (op, 0), mode, false) == 1")))
-
(define_constraint "S"
"@internal
A constant call address."
diff -r d8a511706364 -r a77a09434037 external/gpl3/gcc/dist/gcc/config/riscv/crti.asm
--- a/external/gpl3/gcc/dist/gcc/config/riscv/crti.asm Thu Mar 26 22:20:42 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,42 +0,0 @@
-/* Copyright (C) 2001, 2002 Free Software Foundation, Inc.
-
-This file is part of GCC.
-
-GCC is free software; you can redistribute it and/or modify it under
-the terms of the GNU General Public License as published by the Free
-Software Foundation; either version 3, or (at your option) any later
-version.
-
-GCC is distributed in the hope that it will be useful, but WITHOUT ANY
-WARRANTY; without even the implied warranty of MERCHANTABILITY or
-FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-for more details.
-
-Under Section 7 of GPL version 3, you are granted additional
-permissions described in the GCC Runtime Library Exception, version
-3.1, as published by the Free Software Foundation.
-
-You should have received a copy of the GNU General Public License and
-a copy of the GCC Runtime Library Exception along with this program;
-see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
-<http://www.gnu.org/licenses/>. */
-
-#ifdef __riscv64
-# define SR sd
-#else
-# define SR sw
-#endif
-
- .section .init,"ax",@progbits
- .globl _init
- .type _init,@function
-_init:
- add sp, sp, -8
- SR ra, 0(sp)
-
- .section .fini,"ax",@progbits
- .globl _fini
- .type _fini,@function
-_fini:
- add sp, sp, -8
- SR ra, 0(sp)
diff -r d8a511706364 -r a77a09434037 external/gpl3/gcc/dist/gcc/config/riscv/crtn.asm
--- a/external/gpl3/gcc/dist/gcc/config/riscv/crtn.asm Thu Mar 26 22:20:42 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,38 +0,0 @@
-/* Copyright (C) 2001, 2002 Free Software Foundation, Inc.
-
-This file is part of GCC.
-
-GCC is free software; you can redistribute it and/or modify it under
-the terms of the GNU General Public License as published by the Free
-Software Foundation; either version 3, or (at your option) any later
-version.
-
-GCC is distributed in the hope that it will be useful, but WITHOUT ANY
-WARraNTY; without even the implied warranty of MERCHANTABILITY or
-FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-for more details.
-
-Under Section 7 of GPL version 3, you are granted additional
-permissions described in the GCC Runtime Library Exception, version
-3.1, as published by the Free Software Foundation.
-
-You should have received a copy of the GNU General Public License and
-a copy of the GCC Runtime Library Exception along with this program;
-see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
-<http://www.gnu.org/licenses/>. */
-
-#ifdef __riscv64
-# define LR ld
-#else
-# define LR lw
-#endif
-
- .section .init,"ax",@progbits
- LR ra, 0(sp)
- addi sp, sp, 8
- ret
-
- .section .fini,"ax",@progbits
- LR ra, 0(sp)
- addi sp, sp, 8
- ret
diff -r d8a511706364 -r a77a09434037 external/gpl3/gcc/dist/gcc/config/riscv/default-32.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/external/gpl3/gcc/dist/gcc/config/riscv/default-32.h Fri Mar 27 01:51:34 2015 +0000
@@ -0,0 +1,22 @@
+/* Definitions of target machine for GCC, for RISC-V,
+ defaulting to 32-bit code generation.
+
+ Copyright (C) 1999-2014 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#define TARGET_64BIT_DEFAULT 0
diff -r d8a511706364 -r a77a09434037 external/gpl3/gcc/dist/gcc/config/riscv/div.S
--- a/external/gpl3/gcc/dist/gcc/config/riscv/div.S Thu Mar 26 22:20:42 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,121 +0,0 @@
- .text
- .align 2
-
-#ifndef __riscv64
-/* Our RV64 64-bit routines are equivalent to our RV32 32-bit routines. */
-# define __udivdi3 __udivsi3
-# define __umoddi3 __umodsi3
-# define __divdi3 __divsi3
-# define __moddi3 __modsi3
-#else
- .globl __udivsi3
-__udivsi3:
- /* Compute __udivdi3(a0 << 32, a1 << 32); cast result to uint32_t. */
- sll a0, a0, 32
- sll a1, a1, 32
- move t0, ra
- jal __udivdi3
- sext.w v0, v0
- jr t0
-
- .globl __umodsi3
-__umodsi3:
- /* Compute __udivdi3((uint32_t)a0, (uint32_t)a1); cast v1 to uint32_t. */
- sll a0, a0, 32
- sll a1, a1, 32
- srl a0, a0, 32
- srl a1, a1, 32
- move t0, ra
- jal __udivdi3
- sext.w v0, v1
- jr t0
-
- .globl __modsi3
- __modsi3 = __moddi3
-
- .globl __divsi3
-__divsi3:
- /* Check for special case of INT_MIN/-1. Otherwise, fall into __divdi3. */
- li t0, -1
- beq a1, t0, .L20
-#endif
-
- .globl __divdi3
-__divdi3:
- bltz a0, .L10
- bltz a1, .L11
- /* Since the quotient is positive, fall into __udivdi3. */
-
- .globl __udivdi3
-__udivdi3:
- move v1, a0
- li v0, -1
- beqz a1, .L5
- li a0, 1
- bgeu a1, v1, .L2
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