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[src/trunk]: src/sys/arch/arm/omap Stylistic and non-functional changes from
details: https://anonhg.NetBSD.org/src/rev/cdc35130712c
branches: trunk
changeset: 336719:cdc35130712c
user: skrll <skrll%NetBSD.org@localhost>
date: Fri Mar 13 08:56:35 2015 +0000
description:
Stylistic and non-functional changes from
PR/49622 (Minor enhancements to if_cpsw)
diffstat:
sys/arch/arm/omap/if_cpsw.c | 22 ++++++++++++----------
sys/arch/arm/omap/if_cpswreg.h | 24 ++++++++++++++++++++++--
2 files changed, 34 insertions(+), 12 deletions(-)
diffs (152 lines):
diff -r fc7d855f88c4 -r cdc35130712c sys/arch/arm/omap/if_cpsw.c
--- a/sys/arch/arm/omap/if_cpsw.c Fri Mar 13 08:05:49 2015 +0000
+++ b/sys/arch/arm/omap/if_cpsw.c Fri Mar 13 08:56:35 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_cpsw.c,v 1.9 2015/03/13 08:05:49 skrll Exp $ */
+/* $NetBSD: if_cpsw.c,v 1.10 2015/03/13 08:56:35 skrll Exp $ */
/*
* Copyright (c) 2013 Jonathan A. Kollasch
@@ -53,7 +53,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.9 2015/03/13 08:05:49 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.10 2015/03/13 08:56:35 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -662,7 +662,7 @@
dw[3] |= CPDMA_BD_SOP | CPDMA_BD_OWNER |
MAX(mlen, CPSW_PAD_LEN);
- if (seg == dm->dm_nsegs - 1 && !pad)
+ if ((seg == dm->dm_nsegs - 1) && !pad)
dw[3] |= CPDMA_BD_EOP;
cpsw_set_txdesc(sc, sc->sc_txnext, &bd);
@@ -885,7 +885,7 @@
cpsw_write_4(sc, CPSW_ALE_CONTROL, (3 << 30) | 0x10);
/* Reset and init Sliver port 1 and 2 */
- for (i = 0; i < 2; i++) {
+ for (i = 0; i < CPSW_ETH_PORTS; i++) {
uint32_t macctl;
/* Reset */
@@ -982,9 +982,10 @@
cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_TX);
cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_MISC);
- /* Initialze MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */
+ /* Initialize MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */
/* TODO Calculate MDCLK=CLK/(CLKDIV+1) */
- cpsw_write_4(sc, MDIOCONTROL, (1<<30) | (1<<18) | 0xFF);
+ cpsw_write_4(sc, MDIOCONTROL,
+ MDIOCTL_ENABLE | MDIOCTL_FAULTENB | MDIOCTL_CLKDIV(0xff));
mii_mediachg(mii);
@@ -1045,7 +1046,7 @@
cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1);
while(cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1);
- for (i = 0; i < 2; i++) {
+ for (i = 0; i < CPSW_ETH_PORTS; i++) {
cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1);
while(cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1);
}
@@ -1375,7 +1376,7 @@
}
static void
-cpsw_ale_entry_set(uint32_t *ale_entry, ale_entry_filed_t field, uint32_t val)
+cpsw_ale_entry_set(uint32_t *ale_entry, ale_entry_field_t field, uint32_t val)
{
/* Entry type[61:60] is addr entry(1), Mcast fwd state[63:62] is fw(3)*/
switch (field) {
@@ -1432,7 +1433,8 @@
}
static void
-cpsw_ale_write_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry)
+cpsw_ale_write_entry(struct cpsw_softc *sc, uint16_t idx,
+ const uint32_t *ale_entry)
{
cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]);
cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]);
@@ -1515,7 +1517,7 @@
cpsw_ale_write_entry(sc, 0, ale_entry);
/* Set outgoing MAC Address for Ports 1 and 2. */
- for (i = 1; i < 3; ++i)
+ for (i = CPSW_CPPI_PORTS; i < (CPSW_ETH_PORTS + CPSW_CPPI_PORTS); ++i)
cpsw_ale_set_outgoing_mac(sc, i, mac);
/* Keep the broadcast address at table entry 1. */
diff -r fc7d855f88c4 -r cdc35130712c sys/arch/arm/omap/if_cpswreg.h
--- a/sys/arch/arm/omap/if_cpswreg.h Fri Mar 13 08:05:49 2015 +0000
+++ b/sys/arch/arm/omap/if_cpswreg.h Fri Mar 13 08:56:35 2015 +0000
@@ -29,6 +29,9 @@
#ifndef _IF_CPSWREG_H
#define _IF_CPSWREG_H
+#define CPSW_ETH_PORTS 2
+#define CPSW_CPPI_PORTS 1
+
#define CPSW_SS_OFFSET 0x0000
#define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00)
#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
@@ -88,10 +91,17 @@
#define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04))
#define CPSW_SL_OFFSET 0x0D80
+#define CPSW_SL_IDVER(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x00)
#define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04)
+#define CPSW_SL_MACSTATUS(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x08)
#define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C)
#define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10)
+#define CPSW_SL_BOFFTEST(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x14)
+#define CPSW_SL_RX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x18)
+#define CPSW_SL_TX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x1C)
+#define CPSW_SL_EMCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x20)
#define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24)
+#define CPSW_SL_TX_GAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x28)
#define MDIO_OFFSET 0x1000
#define MDIOCONTROL (MDIO_OFFSET + 0x04)
@@ -117,14 +127,24 @@
#define __BIT32(x) ((uint32_t)__BIT(x))
#define __BITS32(x, y) ((uint32_t)__BITS((x), (y)))
-/* flags for desciptor word 3 */
+/* flags for descriptor word 3 */
#define CPDMA_BD_SOP __BIT32(31)
#define CPDMA_BD_EOP __BIT32(30)
#define CPDMA_BD_OWNER __BIT32(29)
#define CPDMA_BD_EOQ __BIT32(28)
#define CPDMA_BD_TDOWNCMPLT __BIT32(27)
#define CPDMA_BD_PASSCRC __BIT32(26)
+
+#define CPDMA_BD_LONG __BIT32(25) /* Rx descriptor only */
+#define CPDMA_BD_SHORT __BIT32(24)
+#define CPDMA_BD_MAC_CTL __BIT32(23)
+#define CPDMA_BD_OVERRUN __BIT32(22)
#define CPDMA_BD_PKT_ERR_MASK __BITS32(21,20)
+#define CPDMA_BD_RX_VLAN_ENCAP __BIT32(19)
+#define CPDMA_BD_FROM_PORT __BITS32(18,16)
+
+#define CPDMA_BD_TO_PORT_EN __BIT32(20) /* Tx descriptor only */
+#define CPDMA_BD_TO_PORT __BITS32(17,16)
struct cpsw_cpdma_bd {
uint32_t word[4];
@@ -197,7 +217,7 @@
ALE_MCAST_FWD_STATE,
ALE_PORT_MASK,
ALE_PORT_NUMBER,
-} ale_entry_filed_t;
+} ale_entry_field_t;
#define ALE_TYPE_FREE 0
#define ALE_TYPE_ADDRESS 1
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