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[src/trunk]: src/sys/arch/arm/amlogic add dwc2 attachment, doesnt quite work yet
details: https://anonhg.NetBSD.org/src/rev/65a5de44be33
branches: trunk
changeset: 336409:65a5de44be33
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sat Feb 28 15:20:43 2015 +0000
description:
add dwc2 attachment, doesnt quite work yet
diffstat:
sys/arch/arm/amlogic/amlogic_board.c | 118 +++++++++++++++++++++++--
sys/arch/arm/amlogic/amlogic_crureg.h | 19 ++++-
sys/arch/arm/amlogic/amlogic_dwctwo.c | 153 ++++++++++++++++++++++++++++++++++
sys/arch/arm/amlogic/amlogic_intr.h | 4 +-
sys/arch/arm/amlogic/amlogic_io.c | 15 ++-
sys/arch/arm/amlogic/amlogic_reg.h | 12 ++-
sys/arch/arm/amlogic/amlogic_var.h | 9 +-
sys/arch/arm/amlogic/files.amlogic | 13 ++-
8 files changed, 323 insertions(+), 20 deletions(-)
diffs (truncated from 509 to 300 lines):
diff -r afbe9b62a4fe -r 65a5de44be33 sys/arch/arm/amlogic/amlogic_board.c
--- a/sys/arch/arm/amlogic/amlogic_board.c Sat Feb 28 14:10:00 2015 +0000
+++ b/sys/arch/arm/amlogic/amlogic_board.c Sat Feb 28 15:20:43 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: amlogic_board.c,v 1.2 2015/02/27 19:57:10 jmcneill Exp $ */
+/* $NetBSD: amlogic_board.c,v 1.3 2015/02/28 15:20:43 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
#include "opt_amlogic.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amlogic_board.c,v 1.2 2015/02/27 19:57:10 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amlogic_board.c,v 1.3 2015/02/28 15:20:43 jmcneill Exp $");
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/param.h>
@@ -54,13 +54,12 @@
_BUS_DMATAG_FUNCS,
};
-#define CBUS_READ(x) \
- bus_space_read_4(&amlogic_bs_tag, amlogic_core_bsh, (x))
-
-static uint32_t amlogic_get_rate_xtal(void);
-static uint32_t amlogic_get_rate_sys(void);
-static uint32_t amlogic_get_rate_a9(void);
-
+#define CBUS_READ(x) \
+ bus_space_read_4(&amlogic_bs_tag, amlogic_core_bsh, \
+ AMLOGIC_CBUS_OFFSET + (x))
+#define CBUS_WRITE(x, v) \
+ bus_space_write_4(&amlogic_bs_tag, amlogic_core_bsh, \
+ AMLOGIC_CBUS_OFFSET + (x), (v))
void
amlogic_bootstrap(void)
@@ -75,7 +74,7 @@
curcpu()->ci_data.cpu_cc_freq = amlogic_get_rate_a9();
}
-static uint32_t
+uint32_t
amlogic_get_rate_xtal(void)
{
uint32_t ctlreg0;
@@ -85,7 +84,7 @@
return __SHIFTOUT(ctlreg0, PREG_CTLREG0_ADDR_CLKRATE) * 1000000;
}
-static uint32_t
+uint32_t
amlogic_get_rate_sys(void)
{
uint32_t cntl;
@@ -105,7 +104,7 @@
return (uint32_t)clk;
}
-static uint32_t
+uint32_t
amlogic_get_rate_a9(void)
{
uint32_t cntl0, cntl1;
@@ -147,3 +146,98 @@
return rate;
}
+
+uint32_t
+amlogic_get_rate_a9periph(void)
+{
+ const uint32_t cntl1 = CBUS_READ(HHI_SYS_CPU_CLK_CNTL1_REG);
+ const u_int div = __SHIFTOUT(cntl1,
+ HHI_SYS_CPU_CLK_CNTL1_PERIPH_CLK_MUX) + 2;
+
+ return amlogic_get_rate_a9() / div;
+}
+
+void
+amlogic_usbphy_init(int port)
+{
+ bus_space_tag_t bst = &amlogic_bs_tag;
+ bus_space_handle_t bsh = amlogic_core_bsh;
+ bus_size_t ctrl_reg, cfg_reg, gpioao_reg;
+ uint32_t ctrl, cfg, gpioao;
+ u_int pin, pol;
+ bool gpio_power = false, gpio_reset = false;
+
+ gpioao_reg = AMLOGIC_GPIOAO_OFFSET;
+
+ switch (port) {
+ case 0:
+ cfg_reg = PREI_USB_PHY_A_CFG_REG;
+ ctrl_reg = PREI_USB_PHY_A_CTRL_REG;
+ pin = 5;
+ pol = 1;
+ gpio_power = true;
+ break;
+ case 1:
+ cfg_reg = PREI_USB_PHY_B_CFG_REG;
+ ctrl_reg = PREI_USB_PHY_B_CTRL_REG;
+ pin = 4;
+ pol = 0;
+ gpio_reset = true;
+ break;
+ default:
+ return;
+ }
+
+ if (gpio_power) {
+ gpioao = bus_space_read_4(bst, bsh, gpioao_reg);
+ gpioao |= __BIT(pin); /* OEN */
+ if (pol) {
+ gpioao |= __BIT(pin + 16); /* OUT */
+ } else {
+ gpioao &= ~__BIT(pin + 16); /* OUT */
+ }
+ bus_space_write_4(bst, bsh, gpioao_reg, gpioao);
+ }
+
+ CBUS_WRITE(RESET1_REG, RESET1_USB);
+
+ delay(1000);
+
+ cfg = CBUS_READ(cfg_reg);
+ cfg |= PREI_USB_PHY_CFG_CLK_32K_ALT_SEL;
+ CBUS_WRITE(cfg_reg, cfg);
+
+ ctrl = CBUS_READ(ctrl_reg);
+ ctrl &= ~PREI_USB_PHY_CTRL_FSEL;
+ ctrl |= __SHIFTIN(PREI_USB_PHY_CTRL_FSEL_24M,
+ PREI_USB_PHY_CTRL_FSEL);
+ ctrl |= PREI_USB_PHY_CTRL_POR;
+ CBUS_WRITE(ctrl_reg, ctrl);
+
+ delay(1000);
+
+ ctrl = CBUS_READ(ctrl_reg);
+ ctrl &= ~PREI_USB_PHY_CTRL_POR;
+ CBUS_WRITE(ctrl_reg, ctrl);
+
+ delay(50000);
+
+ ctrl = CBUS_READ(ctrl_reg);
+
+ printf("USBPHY: port %d, ctrl %#x\n", port, ctrl);
+
+ if ((ctrl & PREI_USB_PHY_CTRL_CLK_DET) == 0)
+ printf("WARNING: USB PHY port %d clock not detected\n", port);
+
+ if (gpio_reset) {
+ /* Reset */
+ gpioao = bus_space_read_4(bst, bsh, gpioao_reg);
+ gpioao |= __BIT(pin); /* OEN */
+ if (pol) {
+ gpioao |= __BIT(pin + 16); /* OUT */
+ } else {
+ gpioao &= ~__BIT(pin + 16); /* OUT */
+ }
+ bus_space_write_4(bst, bsh, gpioao_reg, gpioao);
+ }
+}
diff -r afbe9b62a4fe -r 65a5de44be33 sys/arch/arm/amlogic/amlogic_crureg.h
--- a/sys/arch/arm/amlogic/amlogic_crureg.h Sat Feb 28 14:10:00 2015 +0000
+++ b/sys/arch/arm/amlogic/amlogic_crureg.h Sat Feb 28 15:20:43 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: amlogic_crureg.h,v 1.2 2015/02/27 21:13:52 jmcneill Exp $ */
+/* $NetBSD: amlogic_crureg.h,v 1.3 2015/02/28 15:20:43 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -33,6 +33,7 @@
#define HHI_SYS_CPU_CLK_CNTL1_REG CBUS_REG(0x1057)
#define HHI_SYS_CPU_CLK_CNTL1_SDIV __BITS(29,20)
+#define HHI_SYS_CPU_CLK_CNTL1_PERIPH_CLK_MUX __BITS(8,6)
#define HHI_SYS_CPU_CLK_CNTL0_REG CBUS_REG(0x1067)
#define HHI_SYS_CPU_CLK_CNTL0_CLKSEL __BIT(7)
@@ -44,9 +45,25 @@
#define HHI_SYS_PLL_CNTL_DIV __BITS(14,9)
#define HHI_SYS_PLL_CNTL_OD __BITS(17,16)
+#define RESET1_REG CBUS_REG(0x1102)
+#define RESET1_USB __BIT(2)
+
#define PREG_CTLREG0_ADDR_REG CBUS_REG(0x2000)
#define PREG_CTLREG0_ADDR_CLKRATE __BITS(9,4)
+#define PREI_USB_PHY_A_CFG_REG CBUS_REG(0x2200)
+#define PREI_USB_PHY_A_CTRL_REG CBUS_REG(0x2201)
+#define PREI_USB_PHY_B_CFG_REG CBUS_REG(0x2208)
+#define PREI_USB_PHY_B_CTRL_REG CBUS_REG(0x2209)
+
+#define PREI_USB_PHY_CFG_CLK_32K_ALT_SEL __BIT(15)
+
+#define PREI_USB_PHY_CTRL_FSEL __BITS(24,22)
+#define PREI_USB_PHY_CTRL_FSEL_24M 5
+#define PREI_USB_PHY_CTRL_FSEL_12M 2
+#define PREI_USB_PHY_CTRL_POR __BIT(15)
+#define PREI_USB_PHY_CTRL_CLK_DET __BIT(8)
+
#define WATCHDOG_TC_REG CBUS_REG(0x2640)
#define WATCHDOG_TC_CPUS __BITS(27,24)
#define WATCHDOG_TC_ENABLE __BIT(19)
diff -r afbe9b62a4fe -r 65a5de44be33 sys/arch/arm/amlogic/amlogic_dwctwo.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/amlogic/amlogic_dwctwo.c Sat Feb 28 15:20:43 2015 +0000
@@ -0,0 +1,153 @@
+/* $NetBSD: amlogic_dwctwo.c,v 1.1 2015/02/28 15:20:43 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2013 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Nick Hudson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: amlogic_dwctwo.c,v 1.1 2015/02/28 15:20:43 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/mutex.h>
+#include <sys/bus.h>
+#include <sys/workqueue.h>
+
+#include <arm/amlogic/amlogic_reg.h>
+#include <arm/amlogic/amlogic_crureg.h>
+#include <arm/amlogic/amlogic_var.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+#include <dev/usb/usbdivar.h>
+#include <dev/usb/usb_mem.h>
+
+#include <dwc2/dwc2var.h>
+
+#include <dwc2/dwc2.h>
+#include "dwc2_core.h"
+
+struct amlogic_dwctwo_softc {
+ struct dwc2_softc sc_dwc2;
+
+ void *sc_ih;
+};
+
+static struct dwc2_core_params amlogic_dwctwo_params = {
+ .otg_cap = 2, /* 0 - HNP/SRP capable */
+ .otg_ver = 1, /* 1 - 2.0 */
+ .dma_enable = 1, /* 1 - DMA (default, if available) */
+ .dma_desc_enable = 1, /* 1 - Descriptor DMA (default, if available) */
+ .speed = 0, /* 0 - High Speed */
+ .enable_dynamic_fifo = 1, /* 1 - Allow dynamic FIFO sizing (default, if available) */
+ .en_multiple_tx_fifo = 1, /* Specifies whether dedicated per-endpoint transmit FIFOs are enabled */
+ .host_rx_fifo_size = 520, /* 520 DWORDs */
+ .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
+ .host_perio_tx_fifo_size = 256, /* 256 DWORDs */
+ .max_transfer_size = 65535,/* 2047 to 65,535 */
+ .max_packet_count = 511, /* 15 to 511 */
+ .host_channels = 8, /* 1 to 16 */
+ .phy_type = 1, /* 1- UTMI+ Phy */
+ .phy_utmi_width = 8, /* 8 bits */
+ .phy_ulpi_ddr = 0, /* Single */
+ .phy_ulpi_ext_vbus = 0,
+ .i2c_enable = 0,
+ .ulpi_fs_ls = 0, /* 0 - No (default) */
+ .host_support_fs_ls_low_power = 0, /* 0 - Don't support low power mode (default) */
+ .host_ls_low_power_phy_clk = 0, /* 1 - 48 MHz default when phy_type is UTMI+ or ULPI*/
+ .ts_dline = 0, /* 0 - No (default) */
+ .reload_ctl = 0, /* 0 - No (default for core < 2.92a) */
+ .ahbcfg = 0x7, /* INCR16 */
+ .uframe_sched = 1, /* True to enable microframe scheduler */
+};
+
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