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[src/trunk]: src/sys Initial Zynq (Xilinx) support
details: https://anonhg.NetBSD.org/src/rev/f49f1da6938c
branches: trunk
changeset: 335779:f49f1da6938c
user: hkenken <hkenken%NetBSD.org@localhost>
date: Fri Jan 23 12:34:09 2015 +0000
description:
Initial Zynq (Xilinx) support
Add support for ZedBoard evaluation board and Parallella board.
* cemac(4) Cadence EMAC/GEM(Gigabit) Ethernet Controller driver
based on at91emac
diffstat:
sys/arch/arm/conf/majors.arm32 | 3 +-
sys/arch/arm/zynq/files.zynq | 58 +
sys/arch/arm/zynq/zynq7000_board.c | 140 +
sys/arch/arm/zynq/zynq7000_intr.h | 103 +
sys/arch/arm/zynq/zynq7000_reg.h | 57 +
sys/arch/arm/zynq/zynq7000_sdhc.c | 119 +
sys/arch/arm/zynq/zynq7000_uart.c | 64 +
sys/arch/arm/zynq/zynq7000_usb.c | 81 +
sys/arch/arm/zynq/zynq7000_var.h | 99 +
sys/arch/arm/zynq/zynq_axi.c | 147 ++
sys/arch/arm/zynq/zynq_cemac.c | 86 +
sys/arch/arm/zynq/zynq_dma.c | 47 +
sys/arch/arm/zynq/zynq_slcr.c | 309 ++++
sys/arch/arm/zynq/zynq_slcrreg.h | 187 ++
sys/arch/arm/zynq/zynq_slcrvar.h | 62 +
sys/arch/arm/zynq/zynq_space.c | 267 +++
sys/arch/arm/zynq/zynq_uart.c | 2192 +++++++++++++++++++++++++++++++
sys/arch/arm/zynq/zynq_uartreg.h | 110 +
sys/arch/arm/zynq/zynq_uartvar.h | 55 +
sys/arch/arm/zynq/zynq_usb.c | 378 +++++
sys/arch/arm/zynq/zynq_usbreg.h | 112 +
sys/arch/arm/zynq/zynq_usbvar.h | 71 +
sys/arch/evbarm/Makefile | 4 +-
sys/arch/evbarm/conf/PARALLELLA | 293 ++++
sys/arch/evbarm/conf/PARALLELLA_INSTALL | 11 +
sys/arch/evbarm/conf/ZEDBOARD | 291 ++++
sys/arch/evbarm/conf/ZEDBOARD_INSTALL | 11 +
sys/arch/evbarm/conf/files.parallella | 4 +
sys/arch/evbarm/conf/files.zedboard | 4 +
sys/arch/evbarm/conf/files.zynq | 12 +
sys/arch/evbarm/conf/mk.zynq | 35 +
sys/arch/evbarm/conf/std.zynq | 34 +
sys/arch/evbarm/zynq/genassym.cf | 47 +
sys/arch/evbarm/zynq/platform.h | 56 +
sys/arch/evbarm/zynq/zynq_machdep.c | 239 +++
sys/arch/evbarm/zynq/zynq_start.S | 321 ++++
sys/dev/cadence/cemacreg.h | 273 +++
sys/dev/cadence/if_cemac.c | 1024 ++++++++++++++
sys/dev/cadence/if_cemacvar.h | 41 +
39 files changed, 7445 insertions(+), 2 deletions(-)
diffs (truncated from 7630 to 300 lines):
diff -r bb6211ad8ad9 -r f49f1da6938c sys/arch/arm/conf/majors.arm32
--- a/sys/arch/arm/conf/majors.arm32 Fri Jan 23 10:19:22 2015 +0000
+++ b/sys/arch/arm/conf/majors.arm32 Fri Jan 23 12:34:09 2015 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: majors.arm32,v 1.35 2014/04/16 22:40:24 matt Exp $
+# $NetBSD: majors.arm32,v 1.36 2015/01/23 12:34:09 hkenken Exp $
#
# Device majors for arm32
#
@@ -106,6 +106,7 @@
device-major twe char 109 twe
device-major nsmb char 110 nsmb
device-major vchiq char 111 vchiq
+device-major zynquart char 112 zynquart
# Majors up to 143 are reserved for machine-dependent drivers.
# New machine-independent driver majors are assigned in
diff -r bb6211ad8ad9 -r f49f1da6938c sys/arch/arm/zynq/files.zynq
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/zynq/files.zynq Fri Jan 23 12:34:09 2015 +0000
@@ -0,0 +1,58 @@
+# $NetBSD: files.zynq,v 1.1 2015/01/23 12:34:09 hkenken Exp $
+#
+# Configuration info for xilinx Zynq-7000 ARM Peripherals
+#
+
+include "arch/arm/pic/files.pic"
+include "arch/arm/cortex/files.cortex"
+
+file arch/arm/zynq/zynq_space.c
+file arch/arm/zynq/zynq_dma.c
+
+file arch/arm/arm32/arm32_boot.c
+file arch/arm/arm32/arm32_kvminit.c
+file arch/arm/arm32/arm32_reboot.c
+file arch/arm/arm32/irq_dispatch.S
+
+file arch/arm/zynq/zynq7000_board.c
+
+# Console parameters
+defflag opt_zynq.h ZYNQ
+defflag opt_zynq.h ZYNQ7000
+defparam opt_zynq.h CONADDR
+defparam opt_zynq.h CONSPEED
+defparam opt_zynq.h CONMODE
+defparam opt_zynq.h MEMSIZE
+
+# AXI bus interface and SoC domains
+device axi {[addr=-1], [size=0], [irq=-1], [irqbase=-1]} : bus_space_generic
+attach axi at mainbus
+file arch/arm/zynq/zynq_axi.c axi
+
+# System Level Control Module
+device zynqslcr
+attach zynqslcr at axi
+file arch/arm/zynq/zynq_slcr.c zynqslcr needs-flag
+
+# UART
+device zynquart
+attach zynquart at axi
+file arch/arm/zynq/zynq_uart.c zynquart needs-flag
+file arch/arm/zynq/zynq7000_uart.c zynquart
+defflag opt_zynquart.h ZYNQUARTCONSOLE
+
+# USB controller
+attach ehci at axi with zynqusb
+file arch/arm/zynq/zynq_usb.c zynqusb
+file arch/arm/zynq/zynq7000_usb.c zynqusb
+
+# SD host controller for SD/MMC
+attach sdhc at axi with sdhc_axi
+file arch/arm/zynq/zynq7000_sdhc.c sdhc_axi
+
+# Gigabit Ethernet Controller
+device cemac: ether, ifnet, arp, mii, bus_dma_generic
+attach cemac at axi
+file dev/cadence/if_cemac.c cemac
+file arch/arm/zynq/zynq_cemac.c cemac
+
diff -r bb6211ad8ad9 -r f49f1da6938c sys/arch/arm/zynq/zynq7000_board.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/zynq/zynq7000_board.c Fri Jan 23 12:34:09 2015 +0000
@@ -0,0 +1,140 @@
+/* $NetBSD: zynq7000_board.c,v 1.1 2015/01/23 12:34:09 hkenken Exp $ */
+/*-
+ * Copyright (c) 2015 Genetec Corporation. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(1, "$NetBSD: zynq7000_board.c,v 1.1 2015/01/23 12:34:09 hkenken Exp $");
+
+#include "opt_zynq.h"
+#include "arml2cc.h"
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+
+#include <arm/locore.h>
+#include <arm/cortex/a9tmr_var.h>
+#include <arm/cortex/pl310_var.h>
+#include <arm/mainbus/mainbus.h>
+
+#include <arm/zynq/zynq7000_var.h>
+#include <arm/zynq/zynq7000_reg.h>
+
+/*
+ * PERIPHCLK_N is an arm root clock divider for MPcore interupt controller.
+ * PERIPHCLK_N is equal to, or greater than two.
+ * see "Cortex-A9 MPCore Technical Reference Manual" -
+ * Chapter 5: Clocks, Resets, and Power Management, 5.1: Clocks.
+ */
+#ifndef PERIPHCLK_N
+#define PERIPHCLK_N 2
+#endif
+
+bus_space_tag_t zynq7000_ioreg_bst = &zynq_bs_tag;
+bus_space_handle_t zynq7000_ioreg_bsh;
+bus_space_tag_t zynq7000_armcore_bst = &zynq_bs_tag;
+bus_space_handle_t zynq7000_armcore_bsh;
+
+struct zynq7000_clock_info clk_info = { 0 };
+
+static void zynq7000_clock_init(struct zynq7000_clock_info *);
+
+psize_t
+zynq7000_memprobe(void)
+{
+ return MEMSIZE * 1024 * 1024;
+}
+
+void
+zynq7000_bootstrap(vaddr_t iobase)
+{
+ int error;
+
+ zynq7000_ioreg_bsh = (bus_space_handle_t) iobase;
+ error = bus_space_map(zynq7000_ioreg_bst, ZYNQ7000_IOREG_PBASE,
+ ZYNQ7000_IOREG_SIZE, 0, &zynq7000_ioreg_bsh);
+ if (error)
+ panic("%s: failed to map Zynq %s registers: %d",
+ __func__, "io", error);
+
+ zynq7000_armcore_bsh = (bus_space_handle_t) iobase + ZYNQ7000_IOREG_SIZE;
+ error = bus_space_map(zynq7000_armcore_bst, ZYNQ7000_ARMCORE_PBASE,
+ ZYNQ7000_ARMCORE_SIZE, 0, &zynq7000_armcore_bsh);
+ if (error)
+ panic("%s: failed to map Zynq %s registers: %d",
+ __func__, "armcore", error);
+
+ struct zynq7000_clock_info * const clk = &clk_info;
+ zynq7000_clock_init(clk);
+
+#if NARML2CC > 0
+ arml2cc_init(zynq7000_armcore_bst, zynq7000_armcore_bsh, ARMCORE_L2C_BASE);
+#endif
+}
+
+static void
+zynq7000_clock_init(struct zynq7000_clock_info *clk)
+{
+ clk->clk_ps = ZYNQ7000_PS_CLK;
+}
+
+void
+zynq7000_device_register(device_t self, void *aux)
+{
+ prop_dictionary_t dict = device_properties(self);
+
+ if (device_is_a(self, "armperiph")
+ && device_is_a(device_parent(self), "mainbus")) {
+ /*
+ * XXX KLUDGE ALERT XXX
+ * The iot mainbus supplies is completely wrong since it scales
+ * addresses by 2. The simpliest remedy is to replace with our
+ * bus space used for the armcore regisers (which armperiph uses).
+ */
+ struct mainbus_attach_args * const mb = aux;
+ mb->mb_iot = zynq7000_armcore_bst;
+ return;
+ }
+
+ /*
+ * We need to tell the A9 Global/Watchdog Timer
+ * what frequency it runs at.
+ */
+ if (device_is_a(self, "a9tmr") || device_is_a(self, "a9wdt")) {
+ prop_dictionary_set_uint32(dict, "frequency",
+ 666666666 / PERIPHCLK_N);
+ return;
+ }
+}
+
+#ifdef MULTIPROCESSOR
+void
+zynq7000_cpu_hatch(struct cpu_info *ci)
+{
+ a9tmr_init_cpu_clock(ci);
+}
+#endif
diff -r bb6211ad8ad9 -r f49f1da6938c sys/arch/arm/zynq/zynq7000_intr.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/zynq/zynq7000_intr.h Fri Jan 23 12:34:09 2015 +0000
@@ -0,0 +1,103 @@
+/* $NetBSD: zynq7000_intr.h,v 1.1 2015/01/23 12:34:09 hkenken Exp $ */
+/*-
+ * Copyright (c) 2015 Genetec Corporation. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_ZYNQ_ZYNQ7000_INTR_H_
+#define _ARM_ZYNQ_ZYNQ7000_INTR_H_
+
+#define PIC_MAXSOURCES 128
+#define PIC_MAXMAXSOURCES 128
+
+/*
+ * The ZYNQ7000 uses a generic interrupt controller so pull that stuff.
+ */
+#include <arm/cortex/gic_intr.h>
+#include <arm/cortex/a9tmr_intr.h> /* A9 Timer PPIs */
+
+
+#define IRQ_CPU0 32
+#define IRQ_CPU1 33
+#define IRQ_L2CC 34
+#define IRQ_OCM 35
+#define IRQ__RSVD36 36
+#define IRQ_PMU0 37
+#define IRQ_PMU1 38
+#define IRQ_XADC 39
+#define IRQ_DVI 40
+#define IRQ_SWDT 41
+#define IRQ_TTC0 42
+#define IRQ__RSVD44 44
+#define IRQ_DMAC_ABORT 45
+#define IRQ_DMAC0 46
+#define IRQ_DMAC1 47
+#define IRQ_DMAC2 48
+#define IRQ_DMAC3 49
+#define IRQ_SMC 50
+#define IRQ_QSPI 51
+#define IRQ_GPIO 52
+#define IRQ_USB0 53
+#define IRQ_ETH0 54
+#define IRQ_ETH0_WU 55
+#define IRQ_SDIO0 56
+#define IRQ_I2C0 57
+#define IRQ_SPI0 58
+#define IRQ_UART0 59
+#define IRQ_CAN0 60
+#define IRQ_FPGA0 60
+#define IRQ_FPGA1 61
+#define IRQ_FPGA2 62
+#define IRQ_FPGA3 64
+#define IRQ_FPGA4 65
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