[src/trunk]: src/sys/arch/arm/allwinner support both MII and RGMII phy types

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/8c055af7a24a
branches:  trunk
changeset: 333072:8c055af7a24a
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Fri Oct 17 20:18:41 2014 +0000

description:
support both MII and RGMII phy types

diffstat:

 sys/arch/arm/allwinner/awin_gige.c |  21 ++++++++++++++++-----
 1 files changed, 16 insertions(+), 5 deletions(-)

diffs (48 lines):

diff -r eb63f0471530 -r 8c055af7a24a sys/arch/arm/allwinner/awin_gige.c
--- a/sys/arch/arm/allwinner/awin_gige.c        Fri Oct 17 20:02:12 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_gige.c        Fri Oct 17 20:18:41 2014 +0000
@@ -31,7 +31,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: awin_gige.c,v 1.8 2014/10/04 15:25:15 martin Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_gige.c,v 1.9 2014/10/17 20:18:41 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -92,6 +92,9 @@
        struct awin_gige_softc * const sc = device_private(self);
        struct awinio_attach_args * const aio = aux;
        const struct awin_locators * const loc = &aio->aio_loc;
+       prop_dictionary_t cfg = device_properties(self);
+       uint32_t clkreg;
+       const char *phy_type;
 
        sc->sc_core.sc_dev = self;
 
@@ -123,13 +126,21 @@
         */
        awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
            AWIN_AHB_GATING1_REG, AWIN_AHB_GATING1_GMAC, 0);
+
        /*
-        * We use RGMII phy mode, set up clock accordingly
+        * PHY clock setup
         */
-       bus_space_write_4(aio->aio_core_bst, aio->aio_ccm_bsh,
-           AWIN_GMAC_CLK_REG, 4); /* GPIT = RMII */
+       if (!prop_dictionary_get_cstring_nocopy(cfg, "phy-type", &phy_type))
+               phy_type = "rgmii";
+       if (strcmp(phy_type, "rgmii")) {
+               clkreg = AWIN_GMAC_CLK_PIT | AWIN_GMAC_CLK_TCS_INT_RGMII;
+       } else if (strcmp(phy_type, "mii")) {
+               clkreg = AWIN_GMAC_CLK_TCS_MII;
+       } else {
+               panic("unknown phy type '%s'", phy_type);
+       }
        awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
-           AWIN_GMAC_CLK_REG, 2, 0); /* GTCS = internal transmit clock */
+           AWIN_GMAC_CLK_REG, clkreg, AWIN_GMAC_CLK_PIT|AWIN_GMAC_CLK_TCS);
 
        dwc_gmac_attach(&sc->sc_core, 2);
 }