[src/trunk]: src/sys/arch/arm/allwinner A31 USB support

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/7a804266c5e8
branches:  trunk
changeset: 332941:7a804266c5e8
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sun Oct 12 13:07:45 2014 +0000

description:
A31 USB support

diffstat:

 sys/arch/arm/allwinner/awin_reg.h |  28 ++++++++++++++++++++++
 sys/arch/arm/allwinner/awin_usb.c |  49 ++++++++++++++++++++++++++++++--------
 2 files changed, 66 insertions(+), 11 deletions(-)

diffs (142 lines):

diff -r 8bcc657ecbf5 -r 7a804266c5e8 sys/arch/arm/allwinner/awin_reg.h
--- a/sys/arch/arm/allwinner/awin_reg.h Sun Oct 12 12:32:15 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_reg.h Sun Oct 12 13:07:45 2014 +0000
@@ -1718,6 +1718,10 @@
 
 #define AWIN_A31_CPU_AXI_CFG_REG               0x0050
 
+#define AWIN_A31_AHB_RESET0_REG                0x02C0
+#define AWIN_A31_AHB_RESET1_REG                0x02C4
+#define AWIN_A31_AHB_RESET2_REG                0x02C8
+
 #define AWIN_A31_CPUCFG_RST_CTRL_CORE_RESET __BIT(1)
 #define AWIN_A31_CPUCFG_RST_CTRL_CPU_RESET __BIT(0)
 
@@ -1738,6 +1742,30 @@
 #define AWIN_A31_USB_CLK_PHY1_ENABLE   __BIT(1)
 #define AWIN_A31_USB_CLK_PHY0_ENABLE   __BIT(0)
 
+#define AWIN_A31_AHB_RESET0_USBOHCI2_RST       __BIT(31)
+#define AWIN_A31_AHB_RESET0_USBOHCI1_RST       __BIT(30)
+#define AWIN_A31_AHB_RESET0_USBOHCI0_RST       __BIT(29)
+#define AWIN_A31_AHB_RESET0_USBEHCI1_RST       __BIT(27)
+#define AWIN_A31_AHB_RESET0_USBEHCI0_RST       __BIT(26)
+#define AWIN_A31_AHB_RESET0_USBOTG_RST         __BIT(24)
+#define AWIN_A31_AHB_RESET0_SPI3_RST           __BIT(23)
+#define AWIN_A31_AHB_RESET0_SPI2_RST           __BIT(22)
+#define AWIN_A31_AHB_RESET0_SPI1_RST           __BIT(21)
+#define AWIN_A31_AHB_RESET0_SPI0_RST           __BIT(20)
+#define AWIN_A31_AHB_RESET0_HSTMR_RST          __BIT(19)
+#define AWIN_A31_AHB_RESET0_TS_RST             __BIT(18)
+#define AWIN_A31_AHB_RESET0_GMAC_RST           __BIT(17)
+#define AWIN_A31_AHB_RESET0_SDRAM_RST          __BIT(14)
+#define AWIN_A31_AHB_RESET0_NAND0_RST          __BIT(13)
+#define AWIN_A31_AHB_RESET0_NAND1_RST          __BIT(12)
+#define AWIN_A31_AHB_RESET0_SD3_RST            __BIT(11)
+#define AWIN_A31_AHB_RESET0_SD2_RST            __BIT(10)
+#define AWIN_A31_AHB_RESET0_SD1_RST            __BIT(9)
+#define AWIN_A31_AHB_RESET0_SD0_RST            __BIT(8)
+#define AWIN_A31_AHB_RESET0_DMA_RST            __BIT(6)
+#define AWIN_A31_AHB_RESET0_SS_RST             __BIT(5)
+#define AWIN_A31_AHB_RESET0_MIPIDSI_RST                __BIT(1)
+
 #define AWIN_A31_WDOG1_IRQ_EN_REG              0x00A0
 #define AWIN_A31_WDOG1_IRQ_STA_REG             0x00A4
 #define AWIN_A31_WDOG1_CTRL_REG                        0x00B0
diff -r 8bcc657ecbf5 -r 7a804266c5e8 sys/arch/arm/allwinner/awin_usb.c
--- a/sys/arch/arm/allwinner/awin_usb.c Sun Oct 12 12:32:15 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_usb.c Sun Oct 12 13:07:45 2014 +0000
@@ -34,7 +34,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: awin_usb.c,v 1.14 2014/10/10 07:36:11 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_usb.c,v 1.15 2014/10/12 13:07:45 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -71,6 +71,7 @@
        bus_space_handle_t usbsc_usb0_phy_csr_bsh;
        u_int usbsc_number;
        struct awin_gpio_pindata usbsc_drv_pin;
+       struct awin_gpio_pindata usbsc_restrict_pin;
 
        device_t usbsc_ohci_dev;
        device_t usbsc_ehci_dev;
@@ -283,6 +284,8 @@
 static int awinusb_ports;
 
 static const char awinusb_drvpin_names[2][8] = { "usb1drv", "usb2drv" };
+static const char awinusb_restrictpin_names[2][13] = { "usb1restrict", "usb2restrict" };
+
 static const bus_size_t awinusb_dram_hpcr_regs[2] = {
        AWIN_DRAM_HPCR_USB1_REG,
        AWIN_DRAM_HPCR_USB2_REG,
@@ -331,6 +334,22 @@
        AWIN_A31_USB_CLK_USBPHY2_ENABLE |
        AWIN_A31_USB_CLK_PHY2_ENABLE,
 };
+static const uint32_t awinusb_usb_ahb_reset_a31[2] = {
+#if NOHCI > 0
+       AWIN_A31_AHB_RESET0_USBOHCI0_RST |
+#endif
+#if NEHCI > 0
+       AWIN_A31_AHB_RESET0_USBEHCI0_RST |
+#endif
+       0,
+#if NOHCI > 0
+       AWIN_A31_AHB_RESET0_USBOHCI1_RST |
+#endif
+#if NEHCI > 0
+       AWIN_A31_AHB_RESET0_USBEHCI1_RST |
+#endif
+       0,
+};
 
 int
 awinusb_match(device_t parent, cfdata_t cf, void *aux)
@@ -374,19 +393,20 @@
        aprint_normal("\n");
 
        if (awin_chip_id() == AWIN_CHIP_ID_A31) {
-               /*
-                * Access to the USB phy is off USB0 so make sure it's on.
-               */
-               awin_reg_set_clear(usbsc->usbsc_bst, aio->aio_ccm_bsh,
-                   AWIN_AHB_GATING0_REG,
-                   awinusb_ahb_gating_a31[loc->loc_port], 0);
-
-               /*
-                * Enable the USB phy for this port.
-                */
+               /* Enable USB PHY */
                awin_reg_set_clear(usbsc->usbsc_bst, aio->aio_ccm_bsh,
                    AWIN_USB_CLK_REG, awinusb_usb_clk_set_a31[loc->loc_port],
                    0);
+
+               /* AHB gate enable */
+               awin_reg_set_clear(usbsc->usbsc_bst, aio->aio_ccm_bsh,
+                   AWIN_AHB_GATING0_REG,
+                   AWIN_A31_AHB_GATING0_USB0 | awinusb_ahb_gating_a31[loc->loc_port],
+                   0);
+
+               /* Soft reset */
+               awin_reg_set_clear(usbsc->usbsc_bst, aio->aio_ccm_bsh,
+                   AWIN_A31_AHB_RESET0_REG, awinusb_usb_ahb_reset_a31[loc->loc_port], 0);
        } else {
                /*
                 * Access to the USB phy is off USB0 so make sure it's on.
@@ -432,6 +452,13 @@
                aprint_error_dev(self, "no power gpio found\n");
        }
 
+       if (awin_gpio_pin_reserve(awinusb_restrictpin_names[loc->loc_port],
+                   &usbsc->usbsc_restrict_pin)) {
+               awin_gpio_pindata_write(&usbsc->usbsc_restrict_pin, 1);
+       } else {
+               aprint_error_dev(self, "no restrict gpio found\n");
+       }
+
        /*
         * Disable interrupts
         */