[src/trunk]: src/sys/arch/arm/allwinner add some more bit definitions

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/42e4b7fa5765
branches:  trunk
changeset: 332677:42e4b7fa5765
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Fri Oct 03 11:21:56 2014 +0000

description:
add some more bit definitions

diffstat:

 sys/arch/arm/allwinner/awin_reg.h |  16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diffs (47 lines):

diff -r 624c824972b0 -r 42e4b7fa5765 sys/arch/arm/allwinner/awin_reg.h
--- a/sys/arch/arm/allwinner/awin_reg.h Fri Oct 03 11:05:36 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_reg.h Fri Oct 03 11:21:56 2014 +0000
@@ -867,6 +867,10 @@
 #define AWIN_PLL2_CFG_FACTOR_N         __BITS(14,8)
 #define AWIN_PLL2_CFG_PREVDIV          __BITS(4,0)
 
+#define AWIN_PLL3_MODE_SEL             __BIT(15)
+#define AWIN_PLL3_FRAC_SET             __BIT(14)
+#define AWIN_PLL3_FACTOR_M             __BITS(6,0)
+
 #define AWIN_PLL5_CFG_DDR_CLK_EN       __BIT(29)
 #define AWIN_PLL5_CFG_LDO_EN           __BIT(7)
 #define AWIN_PLL5_CFG_FACTOR_M1                __BITS(3,2)
@@ -1012,6 +1016,14 @@
 #define AWIN_GMAC_CLK_TCS_EXT_125      1
 #define AWIN_GMAC_CLK_TCS_INT_RGMII    2
 
+#define AWIN_LCDx_CH0_CLK_LCDx_RST     __BIT(30)
+#define AWIN_LCDx_CHx_CLK_SRC_SEL      __BITS(25,24)
+#define AWIN_LCDx_CHx_CLK_SRC_SEL_PLL3 0
+#define AWIN_LCDx_CHx_CLK_SRC_SEL_PLL7 1
+#define AWIN_LCDx_CHx_CLK_SRC_SEL_PLL3_2X 2
+#define AWIN_LCDx_CHx_CLK_SRC_SEL_PLL6_2 3
+#define AWIN_LCDx_CH1_CLK_DIV_RATIO_M  __BITS(3,0)
+
 #define AWIN_HDMI_CLK_SRC_SEL          __BITS(25,24)
 #define AWIN_HDMI_CLK_SRC_SEL_PLL3     0
 #define AWIN_HDMI_CLK_SRC_SEL_PLL7     1
@@ -1019,6 +1031,9 @@
 #define AWIN_HDMI_CLK_SRC_SEL_PLL7_2X  3
 #define AWIN_HDMI_CLK_DIV_RATIO_M      __BITS(3,0)
 
+#define AWIN_SD_CLK_PHASE_CTR          __BITS(22,20)
+#define AWIN_SD_CLK_OUTPUT_PHASE_CTR   __BITS(10,8)
+
 #define AWIN_CLK_OUT_ENABLE            __BIT(31)
 #define AWIN_CLK_OUT_SRC_SEL           __BITS(25,24)
 #define AWIN_CLK_OUT_SRC_SEL_32K       0
@@ -1578,6 +1593,7 @@
 #define AWIN_HDMI_VID_TIMING_3_HSPW    __BITS(11,0)
 
 #define AWIN_HDMI_VID_TIMING_4_TX_CLOCK        __BITS(25,16)
+#define AWIN_HDMI_VID_TIMING_4_TX_CLOCK_NORMAL 0x3e0
 #define AWIN_HDMI_VID_TIMING_4_VSYNC_ACTIVE_SEL __BIT(1)
 #define AWIN_HDMI_VID_TIMING_4_HSYNC_ACTIVE_SEL __BIT(0)