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[src/trunk]: src/sys add DesignWare SD/MMC controller driver
details: https://anonhg.NetBSD.org/src/rev/b69c44c85498
branches: trunk
changeset: 335124:b69c44c85498
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sat Dec 27 01:18:48 2014 +0000
description:
add DesignWare SD/MMC controller driver
diffstat:
sys/conf/files | 7 +-
sys/dev/ic/dwc_mmc.c | 582 +++++++++++++++++++++++++++++++++++++++++++++++
sys/dev/ic/dwc_mmc_reg.h | 172 +++++++++++++
sys/dev/ic/dwc_mmc_var.h | 53 ++++
4 files changed, 813 insertions(+), 1 deletions(-)
diffs (truncated from 840 to 300 lines):
diff -r af50b57d46be -r b69c44c85498 sys/conf/files
--- a/sys/conf/files Fri Dec 26 22:44:54 2014 +0000
+++ b/sys/conf/files Sat Dec 27 01:18:48 2014 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files,v 1.1121 2014/10/31 07:38:36 uebayasi Exp $
+# $NetBSD: files,v 1.1122 2014/12/27 01:18:48 jmcneill Exp $
# @(#)files.newconf 7.5 (Berkeley) 5/10/93
version 20141030
@@ -1264,6 +1264,11 @@
device rtsx: sdmmcbus
file dev/ic/rtsx.c rtsx
+# DesignWare SD/MMC host controller
+defflag opt_dwc_mmc.h DWC_MMC_DEBUG
+device dwcmmc: sdmmcbus
+file dev/ic/dwc_mmc.c dwcmmc
+
# Myson MTD803 3-in-1 Fast Ethernet Controller
device mtd: arp, ether, ifnet, mii
file dev/ic/mtd803.c mtd
diff -r af50b57d46be -r b69c44c85498 sys/dev/ic/dwc_mmc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/dev/ic/dwc_mmc.c Sat Dec 27 01:18:48 2014 +0000
@@ -0,0 +1,582 @@
+/* $NetBSD: dwc_mmc.c,v 1.1 2014/12/27 01:18:48 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2014 Jared D. McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "opt_dwc_mmc.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: dwc_mmc.c,v 1.1 2014/12/27 01:18:48 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+
+#include <dev/sdmmc/sdmmcvar.h>
+#include <dev/sdmmc/sdmmcchip.h>
+#include <dev/sdmmc/sdmmc_ioreg.h>
+
+#include <dev/ic/dwc_mmc_reg.h>
+#include <dev/ic/dwc_mmc_var.h>
+
+static int dwc_mmc_host_reset(sdmmc_chipset_handle_t);
+static uint32_t dwc_mmc_host_ocr(sdmmc_chipset_handle_t);
+static int dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t);
+static int dwc_mmc_card_detect(sdmmc_chipset_handle_t);
+static int dwc_mmc_write_protect(sdmmc_chipset_handle_t);
+static int dwc_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t);
+static int dwc_mmc_bus_clock(sdmmc_chipset_handle_t, int);
+static int dwc_mmc_bus_width(sdmmc_chipset_handle_t, int);
+static int dwc_mmc_bus_rod(sdmmc_chipset_handle_t, int);
+static void dwc_mmc_exec_command(sdmmc_chipset_handle_t,
+ struct sdmmc_command *);
+static void dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t, int);
+static void dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t);
+
+static int dwc_mmc_set_clock(struct dwc_mmc_softc *, u_int);
+static int dwc_mmc_update_clock(struct dwc_mmc_softc *);
+static int dwc_mmc_wait_rint(struct dwc_mmc_softc *, uint32_t, int);
+static int dwc_mmc_pio_wait(struct dwc_mmc_softc *,
+ struct sdmmc_command *);
+static int dwc_mmc_pio_transfer(struct dwc_mmc_softc *,
+ struct sdmmc_command *);
+
+void dwc_mmc_dump_regs(void);
+
+static struct sdmmc_chip_functions dwc_mmc_chip_functions = {
+ .host_reset = dwc_mmc_host_reset,
+ .host_ocr = dwc_mmc_host_ocr,
+ .host_maxblklen = dwc_mmc_host_maxblklen,
+ .card_detect = dwc_mmc_card_detect,
+ .write_protect = dwc_mmc_write_protect,
+ .bus_power = dwc_mmc_bus_power,
+ .bus_clock = dwc_mmc_bus_clock,
+ .bus_width = dwc_mmc_bus_width,
+ .bus_rod = dwc_mmc_bus_rod,
+ .exec_command = dwc_mmc_exec_command,
+ .card_enable_intr = dwc_mmc_card_enable_intr,
+ .card_intr_ack = dwc_mmc_card_intr_ack,
+};
+
+#define MMC_WRITE(sc, reg, val) \
+ bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+#define MMC_READ(sc, reg) \
+ bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+
+void
+dwc_mmc_init(struct dwc_mmc_softc *sc)
+{
+ struct sdmmcbus_attach_args saa;
+
+ mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO);
+ cv_init(&sc->sc_intr_cv, "dwcmmcirq");
+
+ dwc_mmc_host_reset(sc);
+ dwc_mmc_bus_width(sc, 1);
+ dwc_mmc_bus_clock(sc, 400);
+
+ memset(&saa, 0, sizeof(saa));
+ saa.saa_busname = "sdmmc";
+ saa.saa_sct = &dwc_mmc_chip_functions;
+ saa.saa_sch = sc;
+ saa.saa_clkmin = 400;
+ saa.saa_clkmax = 25000;
+ saa.saa_caps = SMC_CAPS_4BIT_MODE|
+ SMC_CAPS_8BIT_MODE|
+ SMC_CAPS_SD_HIGHSPEED|
+ SMC_CAPS_MMC_HIGHSPEED|
+ SMC_CAPS_AUTO_STOP;
+#if notyet
+ saa.saa_dmat = sc->sc_dmat;
+ saa.saa_caps |= SMC_CAPS_DMA|
+ SMC_CAPS_MULTI_SEG_DMA;
+#endif
+
+ sc->sc_sdmmc_dev = config_found(sc->sc_dev, &saa, NULL);
+}
+
+int
+dwc_mmc_intr(void *priv)
+{
+ struct dwc_mmc_softc *sc = priv;
+ uint32_t mint, rint;
+
+ mutex_enter(&sc->sc_intr_lock);
+ rint = MMC_READ(sc, DWC_MMC_RINTSTS_REG);
+ mint = MMC_READ(sc, DWC_MMC_MINTSTS_REG);
+ if (!rint && !mint) {
+ mutex_exit(&sc->sc_intr_lock);
+ return 0;
+ }
+ MMC_WRITE(sc, DWC_MMC_RINTSTS_REG, rint);
+ MMC_WRITE(sc, DWC_MMC_MINTSTS_REG, mint);
+
+#ifdef DWC_MMC_DEBUG
+ device_printf(sc->sc_dev, "mint %#x rint %#x\n", mint, rint);
+#endif
+
+ if (rint & DWC_MMC_INT_CARDDET) {
+ rint &= ~DWC_MMC_INT_CARDDET;
+ if (sc->sc_sdmmc_dev) {
+ sdmmc_needs_discover(sc->sc_sdmmc_dev);
+ }
+ }
+
+ if (rint) {
+ sc->sc_intr_rint |= rint;
+ cv_broadcast(&sc->sc_intr_cv);
+ }
+
+ mutex_exit(&sc->sc_intr_lock);
+
+ return 1;
+}
+
+static int
+dwc_mmc_set_clock(struct dwc_mmc_softc *sc, u_int freq)
+{
+ u_int pll_freq = sc->sc_clock_freq / 1000;
+ u_int n = howmany(pll_freq, freq) >> 1;
+
+#ifdef DWC_MMC_DEBUG
+ device_printf(sc->sc_dev, "%s: n=%u freq=%u\n",
+ __func__, n, n ? pll_freq / (2 * n) : pll_freq);
+#endif
+
+ MMC_WRITE(sc, DWC_MMC_CLKDIV_REG,
+ __SHIFTIN(n, DWC_MMC_CLKDIV_CLK_DIVIDER0));
+
+ return dwc_mmc_update_clock(sc);
+}
+
+static int
+dwc_mmc_update_clock(struct dwc_mmc_softc *sc)
+{
+ uint32_t cmd;
+ int retry;
+
+ cmd = DWC_MMC_CMD_START_CMD |
+ DWC_MMC_CMD_UPDATE_CLOCK_REGS_ONLY |
+ DWC_MMC_CMD_WAIT_PRVDATA_COMPLETE;
+
+ if (sc->sc_flags & DWC_MMC_F_USE_HOLD_REG)
+ cmd |= DWC_MMC_CMD_USE_HOLD_REG;
+
+ MMC_WRITE(sc, DWC_MMC_CMD_REG, cmd);
+ retry = 0xfffff;
+ while (--retry > 0) {
+ cmd = MMC_READ(sc, DWC_MMC_CMD_REG);
+ if ((cmd & DWC_MMC_CMD_START_CMD) == 0)
+ break;
+ delay(10);
+ }
+
+ if (retry == 0) {
+ device_printf(sc->sc_dev, "timeout updating clock\n");
+ return ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int
+dwc_mmc_wait_rint(struct dwc_mmc_softc *sc, uint32_t mask, int timeout)
+{
+ int retry, error;
+
+ KASSERT(mutex_owned(&sc->sc_intr_lock));
+
+ if (sc->sc_intr_rint & mask)
+ return 0;
+
+ retry = timeout / hz;
+
+ while (retry > 0) {
+ error = cv_timedwait(&sc->sc_intr_cv, &sc->sc_intr_lock, hz);
+ if (error && error != EWOULDBLOCK)
+ return error;
+ if (sc->sc_intr_rint & mask)
+ return 0;
+ --retry;
+ }
+
+ return ETIMEDOUT;
+}
+
+static int
+dwc_mmc_pio_wait(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd)
+{
+ int retry = 0xfffff;
+ uint32_t bit = (cmd->c_flags & SCF_CMD_READ) ?
+ DWC_MMC_STATUS_FIFO_EMPTY : DWC_MMC_STATUS_FIFO_FULL;
+
+ while (--retry > 0) {
+ uint32_t status = MMC_READ(sc, DWC_MMC_STATUS_REG);
+ if (!(status & bit))
+ return 0;
+ delay(10);
+ }
+
+#ifdef DWC_MMC_DEBUG
+ device_printf(sc->sc_dev, "%s: timed out\n", __func__);
+#endif
+
+ return ETIMEDOUT;
+}
+
+static int
+dwc_mmc_pio_transfer(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd)
+{
+ uint32_t *datap = (uint32_t *)cmd->c_data;
+ int i;
+
+ for (i = 0; i < (cmd->c_resid >> 2); i++) {
+ if (dwc_mmc_pio_wait(sc, cmd))
+ return ETIMEDOUT;
+ if (cmd->c_flags & SCF_CMD_READ) {
+ datap[i] = MMC_READ(sc, DWC_MMC_FIFO_BASE_REG);
+ } else {
+ MMC_WRITE(sc, DWC_MMC_FIFO_BASE_REG, datap[i]);
+ }
+ }
+
+ return 0;
+}
+
+static int
+dwc_mmc_host_reset(sdmmc_chipset_handle_t sch)
+{
+ struct dwc_mmc_softc *sc = sch;
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