[src/trunk]: src/sys/arch/arm/allwinner - Write the correct value to the ctrl...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/a8db6602e88b
branches:  trunk
changeset: 333986:a8db6602e88b
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Tue Nov 25 00:06:32 2014 +0000

description:
- Write the correct value to the ctrl register to restart the watchdog.
  Watchdog restart bit is 0 not 1, and we need to write a key as well.
- Add A31 support.

diffstat:

 sys/arch/arm/allwinner/awin_reg.h |   5 ++-
 sys/arch/arm/allwinner/awin_wdt.c |  78 +++++++++++++++++++++++++++++++++-----
 2 files changed, 71 insertions(+), 12 deletions(-)

diffs (164 lines):

diff -r dc1c3dce6834 -r a8db6602e88b sys/arch/arm/allwinner/awin_reg.h
--- a/sys/arch/arm/allwinner/awin_reg.h Mon Nov 24 21:49:17 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_reg.h Tue Nov 25 00:06:32 2014 +0000
@@ -1503,7 +1503,9 @@
 #define AWIN_CNT64_CTRL_RL_ENABLE      __BIT(1)
 #define AWIN_CNT64_CTRL_CLR_ENABLE     __BIT(0)
 
-#define AWIN_WDOG_CTRL_RSTART          __BIT(1)
+#define AWIN_WDOG_CTRL_KEY             __BITS(12,1)
+#define AWIN_WDOG_CTRL_KEY_MAGIC       0xa57
+#define AWIN_WDOG_CTRL_RSTART          __BIT(0)
 #define AWIN_WDOG_MODE_INTV            __BITS(6,3)
 #define AWIN_WDOG_MODE_INTV_HALFSEC    0
 #define AWIN_WDOG_MODE_INTV_1SEC       1
@@ -2161,6 +2163,7 @@
 #define AWIN_A31_WDOG_CFG_CONFIG_INT           2
 
 #define AWIN_A31_WDOG_MODE_EN                  __BIT(0)
+#define AWIN_A31_WDOG_MODE_INTV                        __BITS(7,4)
 
 #define AWIN_A31_MMC_FIFO                      0x0200
 
diff -r dc1c3dce6834 -r a8db6602e88b sys/arch/arm/allwinner/awin_wdt.c
--- a/sys/arch/arm/allwinner/awin_wdt.c Mon Nov 24 21:49:17 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_wdt.c Tue Nov 25 00:06:32 2014 +0000
@@ -33,7 +33,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: awin_wdt.c,v 1.4 2014/10/10 07:36:11 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_wdt.c,v 1.5 2014/11/25 00:06:32 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -78,6 +78,26 @@
        [16] = __SHIFTIN(AWIN_WDOG_MODE_INTV_16SEC, AWIN_WDOG_MODE_INTV),
 };
 
+static const uint8_t period_map_a31[] = {
+       [0] = __SHIFTIN(AWIN_WDOG_MODE_INTV_1SEC, AWIN_A31_WDOG_MODE_INTV),
+       [1] = __SHIFTIN(AWIN_WDOG_MODE_INTV_1SEC, AWIN_A31_WDOG_MODE_INTV),
+       [2] = __SHIFTIN(AWIN_WDOG_MODE_INTV_2SEC, AWIN_A31_WDOG_MODE_INTV),
+       [3] = __SHIFTIN(AWIN_WDOG_MODE_INTV_3SEC, AWIN_A31_WDOG_MODE_INTV),
+       [4] = __SHIFTIN(AWIN_WDOG_MODE_INTV_4SEC, AWIN_A31_WDOG_MODE_INTV),
+       [5] = __SHIFTIN(AWIN_WDOG_MODE_INTV_5SEC, AWIN_A31_WDOG_MODE_INTV),
+       [6] = __SHIFTIN(AWIN_WDOG_MODE_INTV_6SEC, AWIN_A31_WDOG_MODE_INTV),
+       [7] = __SHIFTIN(AWIN_WDOG_MODE_INTV_8SEC, AWIN_A31_WDOG_MODE_INTV),
+       [8] = __SHIFTIN(AWIN_WDOG_MODE_INTV_8SEC, AWIN_A31_WDOG_MODE_INTV),
+       [9] = __SHIFTIN(AWIN_WDOG_MODE_INTV_10SEC, AWIN_A31_WDOG_MODE_INTV),
+       [10] = __SHIFTIN(AWIN_WDOG_MODE_INTV_10SEC, AWIN_A31_WDOG_MODE_INTV),
+       [11] = __SHIFTIN(AWIN_WDOG_MODE_INTV_12SEC, AWIN_A31_WDOG_MODE_INTV),
+       [12] = __SHIFTIN(AWIN_WDOG_MODE_INTV_12SEC, AWIN_A31_WDOG_MODE_INTV),
+       [13] = __SHIFTIN(AWIN_WDOG_MODE_INTV_14SEC, AWIN_A31_WDOG_MODE_INTV),
+       [14] = __SHIFTIN(AWIN_WDOG_MODE_INTV_14SEC, AWIN_A31_WDOG_MODE_INTV),
+       [15] = __SHIFTIN(AWIN_WDOG_MODE_INTV_16SEC, AWIN_A31_WDOG_MODE_INTV),
+       [16] = __SHIFTIN(AWIN_WDOG_MODE_INTV_16SEC, AWIN_A31_WDOG_MODE_INTV),
+};
+
 static struct awin_wdt_softc {
        device_t sc_dev;
        bus_space_tag_t sc_bst;
@@ -86,6 +106,8 @@
         u_int sc_wdog_period;
         bool sc_wdog_armed;
        uint32_t sc_wdog_mode;
+       bus_size_t sc_ctrl_reg;
+       bus_size_t sc_mode_reg;
 } awin_wdt_sc = {
        .sc_bst = &awin_bs_tag,
        .sc_wdog_period = AWIN_WDT_PERIOD_DEFAULT,
@@ -95,8 +117,11 @@
 awin_wdt_tickle(struct sysmon_wdog *smw)
 {
        struct awin_wdt_softc * const sc = smw->smw_cookie;
-       bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_WDOG_CTRL_REG,
+
+       bus_space_write_4(sc->sc_bst, sc->sc_bsh, sc->sc_ctrl_reg,
+           __SHIFTIN(AWIN_WDOG_CTRL_KEY_MAGIC, AWIN_WDOG_CTRL_KEY) |
            AWIN_WDOG_CTRL_RSTART);
+
        return 0;
 }
 
@@ -104,6 +129,16 @@
 awin_wdt_setmode(struct sysmon_wdog *smw)
 {
        struct awin_wdt_softc * const sc = smw->smw_cookie;
+       const uint8_t *map;
+       size_t mapsize;
+
+       if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+               map = period_map_a31;
+               mapsize = __arraycount(period_map_a31);
+       } else {
+               map = period_map;
+               mapsize = __arraycount(period_map);
+       }
 
        if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
                /*
@@ -113,26 +148,39 @@
        }
 
        if (sc->sc_wdog_armed && smw->smw_period == sc->sc_wdog_period) {
-               bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_WDOG_MODE_REG,
+               if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+                       bus_space_write_4(sc->sc_bst, sc->sc_bsh,
+                           AWIN_A31_WDOG1_CFG_REG,
+                           __SHIFTIN(AWIN_A31_WDOG_CFG_CONFIG_SYS,
+                                     AWIN_A31_WDOG_CFG_CONFIG));
+               }
+               bus_space_write_4(sc->sc_bst, sc->sc_bsh, sc->sc_mode_reg,
                    sc->sc_wdog_mode);
-               bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_WDOG_CTRL_REG,
-                   AWIN_WDOG_CTRL_RSTART);
+               awin_wdt_tickle(smw);
                return 0;
        }
-       if (smw->smw_period > __arraycount(period_map)) {
+       if (smw->smw_period > mapsize) {
                return EINVAL;
        }
        if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
                smw->smw_period = AWIN_WDT_PERIOD_DEFAULT;
                sc->sc_wdog_period = AWIN_WDT_PERIOD_DEFAULT;
        }
-       sc->sc_wdog_mode = AWIN_WDOG_MODE_EN | AWIN_WDOG_MODE_RST_EN
-           | period_map[sc->sc_wdog_period];
+       sc->sc_wdog_mode = AWIN_WDOG_MODE_EN | map[sc->sc_wdog_period];
+       if (awin_chip_id() == AWIN_CHIP_ID_A20 ||
+           awin_chip_id() == AWIN_CHIP_ID_A10) {
+               sc->sc_wdog_mode |= AWIN_WDOG_MODE_RST_EN;
+       }
 
-       bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_WDOG_MODE_REG,
+       if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+               bus_space_write_4(sc->sc_bst, sc->sc_bsh,
+                   AWIN_A31_WDOG1_CFG_REG,
+                   __SHIFTIN(AWIN_A31_WDOG_CFG_CONFIG_SYS,
+                             AWIN_A31_WDOG_CFG_CONFIG));
+       }
+       bus_space_write_4(sc->sc_bst, sc->sc_bsh, sc->sc_mode_reg,
            sc->sc_wdog_mode);
-       bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_WDOG_CTRL_REG,
-           AWIN_WDOG_CTRL_RSTART);
+       awin_wdt_tickle(smw);
        return 0;
 }
 
@@ -168,6 +216,14 @@
        sc->sc_dev = self;
        sc->sc_wdog_armed = (device_cfdata(self)->cf_flags & 1) != 0;
 
+       if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+               sc->sc_ctrl_reg = AWIN_A31_WDOG1_CTRL_REG;
+               sc->sc_mode_reg = AWIN_A31_WDOG1_MODE_REG;
+       } else {
+               sc->sc_ctrl_reg = AWIN_WDOG_CTRL_REG;
+               sc->sc_mode_reg = AWIN_WDOG_MODE_REG;
+       }
+
        sc->sc_bst = aio->aio_core_bst;
        bus_space_subregion(sc->sc_bst, aio->aio_core_bsh,
            loc->loc_offset, loc->loc_size, &sc->sc_bsh);