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[src/trunk]: src/sys/arch Add A80 PIO L, M, N and A80 CIR (RX) support.
details: https://anonhg.NetBSD.org/src/rev/10d8692d36ee
branches: trunk
changeset: 334805:10d8692d36ee
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sun Dec 07 18:32:13 2014 +0000
description:
Add A80 PIO L,M,N and A80 CIR (RX) support.
diffstat:
sys/arch/arm/allwinner/awin_board.c | 15 ++++++++++-
sys/arch/arm/allwinner/awin_gpio.c | 47 +++++++++++++++++++++++++++++++-----
sys/arch/arm/allwinner/awin_intr.h | 3 +-
sys/arch/arm/allwinner/awin_io.c | 6 ++--
sys/arch/arm/allwinner/awin_ir.c | 47 ++++++++++++++++++++++++++++++++----
sys/arch/arm/allwinner/awin_reg.h | 17 +++++++++++++
sys/arch/arm/allwinner/awin_var.h | 5 +++-
sys/arch/evbarm/awin/awin_start.S | 14 ++++++++++-
sys/arch/evbarm/conf/ALLWINNER_A80 | 6 ++--
9 files changed, 136 insertions(+), 24 deletions(-)
diffs (truncated from 406 to 300 lines):
diff -r 7a158b8d4db5 -r 10d8692d36ee sys/arch/arm/allwinner/awin_board.c
--- a/sys/arch/arm/allwinner/awin_board.c Sun Dec 07 16:20:33 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_board.c Sun Dec 07 18:32:13 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_board.c,v 1.32 2014/12/07 15:00:37 jmcneill Exp $ */
+/* $NetBSD: awin_board.c,v 1.33 2014/12/07 18:32:13 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -36,7 +36,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.32 2014/12/07 15:00:37 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.33 2014/12/07 18:32:13 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -58,6 +58,9 @@
#include <arm/cortex/gtmr_var.h>
bus_space_handle_t awin_core_bsh;
+#if defined(ALLWINNER_A80)
+bus_space_handle_t awin_rcpus_bsh;
+#endif
struct arm32_bus_dma_tag awin_dma_tag = {
_BUS_DMAMAP_FUNCS,
@@ -190,6 +193,14 @@
__func__, "io", error);
KASSERT(awin_core_bsh == iobase);
+#ifdef ALLWINNER_A80
+ error = bus_space_map(&awin_bs_tag, AWIN_A80_RCPUS_PBASE,
+ AWIN_A80_RCPUS_SIZE, 0, &awin_rcpus_bsh);
+ if (error)
+ panic("%s: failed to map awin %s registers: %d",
+ __func__, "rcpus", error);
+#endif
+
#ifdef VERBOSE_INIT_ARM
printf("CPU Speed is");
#endif
diff -r 7a158b8d4db5 -r 10d8692d36ee sys/arch/arm/allwinner/awin_gpio.c
--- a/sys/arch/arm/allwinner/awin_gpio.c Sun Dec 07 16:20:33 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_gpio.c Sun Dec 07 18:32:13 2014 +0000
@@ -35,7 +35,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_gpio.c,v 1.15 2014/12/05 11:53:43 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_gpio.c,v 1.16 2014/12/07 18:32:13 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -226,6 +226,17 @@
.grp_pin_mask = 0,
.grp_nc_name = "nc-pm",
},
+ [13] = {
+ .grp_offset = 0,
+ .grp_gc_tag = {
+ .gp_cookie = &pin_groups[13],
+ .gp_pin_read = awin_gpio_pin_read,
+ .gp_pin_write = awin_gpio_pin_write,
+ .gp_pin_ctl = awin_gpio_pin_ctl,
+ },
+ .grp_pin_mask = 0,
+ .grp_nc_name = "nc-pn",
+ },
};
@@ -448,6 +459,8 @@
pin_groups[12].grp_offset = AWIN_A31_CPUPIO_OFFSET +
1 * AWIN_PIO_GRP_SIZE;
pin_groups[12].grp_pin_mask = __BIT(AWIN_A31_PIO_PM_PINS) - 1;
+ pin_groups[13].grp_offset = 0; /* PN */
+ pin_groups[13].grp_pin_mask = 0; /* PN */
} else if (awin_chip_id() == AWIN_CHIP_ID_A80) {
pin_groups[0].grp_pin_mask = __BIT(AWIN_A80_PIO_PA_PINS) - 1;
pin_groups[0].grp_offset = AWIN_A80_PIO_OFFSET +
@@ -479,10 +492,15 @@
pin_groups[9].grp_pin_mask = 0; /* PJ */
pin_groups[10].grp_offset = 0; /* PK */
pin_groups[10].grp_pin_mask = 0; /* PK */
- pin_groups[11].grp_offset = 0; /* PL */
- pin_groups[11].grp_pin_mask = 0; /* PL */
- pin_groups[12].grp_offset = 0; /* PM */
- pin_groups[12].grp_pin_mask = 0; /* PM */
+ pin_groups[11].grp_offset = AWIN_A80_RPIO_OFFSET +
+ 0 * AWIN_PIO_GRP_SIZE;
+ pin_groups[11].grp_pin_mask = __BIT(AWIN_A80_PIO_PL_PINS) - 1;
+ pin_groups[12].grp_offset = AWIN_A80_RPIO_OFFSET +
+ 1 * AWIN_PIO_GRP_SIZE;
+ pin_groups[12].grp_pin_mask = __BIT(AWIN_A80_PIO_PM_PINS) - 1;
+ pin_groups[13].grp_offset = AWIN_A80_RPIO_OFFSET +
+ 2 * AWIN_PIO_GRP_SIZE;
+ pin_groups[13].grp_pin_mask = __BIT(AWIN_A80_PIO_PN_PINS) - 1;
}
for (u_int i = 0; i < __arraycount(pin_groups); i++) {
@@ -491,8 +509,16 @@
if (grp->grp_offset == 0)
continue;
- bus_space_subregion(sc->sc_bst, awin_core_bsh,
- grp->grp_offset, AWIN_PIO_GRP_SIZE, &grp->grp_bsh);
+#if defined(ALLWINNER_A80)
+ if (i >= 11) {
+ bus_space_subregion(sc->sc_bst, awin_rcpus_bsh,
+ grp->grp_offset, AWIN_PIO_GRP_SIZE, &grp->grp_bsh);
+ } else
+#endif
+ {
+ bus_space_subregion(sc->sc_bst, awin_core_bsh,
+ grp->grp_offset, AWIN_PIO_GRP_SIZE, &grp->grp_bsh);
+ }
for (u_int j = 0; j < 4; j++) {
grp->grp_cfg.cfg[j] = bus_space_read_4(sc->sc_bst,
@@ -538,6 +564,10 @@
KASSERT(
('A' <= req->pinset_group && req->pinset_group <= 'I') ||
('L' <= req->pinset_group && req->pinset_group <= 'M'));
+ } else if (awin_chip_id() == AWIN_CHIP_ID_A80) {
+ KASSERT(
+ ('A' <= req->pinset_group && req->pinset_group <= 'I') ||
+ ('L' <= req->pinset_group && req->pinset_group <= 'N'));
} else {
KASSERT('A' <= req->pinset_group && req->pinset_group <= 'I');
}
@@ -744,6 +774,9 @@
if (awin_chip_id() == AWIN_CHIP_ID_A31) {
KASSERT(('A' <= pin_data[2] && pin_data[2] <= 'I') ||
('L' <= pin_data[2] && pin_data[2] <= 'M'));
+ } else if (awin_chip_id() == AWIN_CHIP_ID_A80) {
+ KASSERT(('A' <= pin_data[2] && pin_data[2] <= 'I') ||
+ ('L' <= pin_data[2] && pin_data[2] <= 'N'));
} else {
KASSERT('A' <= pin_data[2] && pin_data[2] <= 'I');
}
diff -r 7a158b8d4db5 -r 10d8692d36ee sys/arch/arm/allwinner/awin_intr.h
--- a/sys/arch/arm/allwinner/awin_intr.h Sun Dec 07 16:20:33 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_intr.h Sun Dec 07 18:32:13 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_intr.h,v 1.13 2014/12/07 00:36:26 jmcneill Exp $ */
+/* $NetBSD: awin_intr.h,v 1.14 2014/12/07 18:32:13 jmcneill Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -198,6 +198,7 @@
#define AWIN_A80_IRQ_WATCHDOG 56
#define AWIN_A80_IRQ_KEYADC 62
#define AWIN_A80_IRQ_NMI 64
+#define AWIN_A80_IRQ_R_CIR 69
#define AWIN_A80_IRQ_R_RSB 71
#define AWIN_A80_IRQ_DMA 82
#define AWIN_A80_IRQ_HSTIMER0 83
diff -r 7a158b8d4db5 -r 10d8692d36ee sys/arch/arm/allwinner/awin_io.c
--- a/sys/arch/arm/allwinner/awin_io.c Sun Dec 07 16:20:33 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_io.c Sun Dec 07 18:32:13 2014 +0000
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.38 2014/12/07 00:36:26 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.39 2014/12/07 18:32:13 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -182,6 +182,7 @@
{ "awinir", OFFANDSIZE(IR0), 0, AWIN_IRQ_IR0, A10|A20 },
{ "awinir", OFFANDSIZE(IR1), 1, AWIN_IRQ_IR1, A10|A20 },
{ "awinir", OFFANDSIZE(A31_CIR), NOPORT, AWIN_A31_IRQ_CIR, A31 },
+ { "awinir", OFFANDSIZE(A80_CIR), NOPORT, AWIN_A80_IRQ_R_CIR, A80 },
};
static int
@@ -221,14 +222,13 @@
switch (awin_chip_id()) {
#ifdef ALLWINNER_A80
case AWIN_CHIP_ID_A80:
+ sc->sc_a80_rcpus_bsh = awin_rcpus_bsh;
bus_space_subregion(sc->sc_bst, sc->sc_bsh,
AWIN_A80_CCU_SCLK_OFFSET, 0x1000, &sc->sc_ccm_bsh);
bus_space_map(sc->sc_bst, AWIN_A80_USB_PBASE,
AWIN_A80_USB_SIZE, 0, &sc->sc_a80_usb_bsh);
bus_space_map(sc->sc_bst, AWIN_A80_CORE2_PBASE,
AWIN_A80_CORE2_SIZE, 0, &sc->sc_a80_core2_bsh);
- bus_space_map(sc->sc_bst, AWIN_A80_RCPUS_PBASE,
- AWIN_A80_RCPUS_SIZE, 0, &sc->sc_a80_rcpus_bsh);
break;
#endif
default:
diff -r 7a158b8d4db5 -r 10d8692d36ee sys/arch/arm/allwinner/awin_ir.c
--- a/sys/arch/arm/allwinner/awin_ir.c Sun Dec 07 16:20:33 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_ir.c Sun Dec 07 18:32:13 2014 +0000
@@ -1,4 +1,6 @@
-/* $NetBSD: awin_ir.c,v 1.4 2014/11/15 14:56:18 jmcneill Exp $ */
+/* $NetBSD: awin_ir.c,v 1.5 2014/12/07 18:32:13 jmcneill Exp $ */
+
+#define AWIN_IR_DEBUG
/*-
* Copyright (c) 2014 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +31,7 @@
#include "opt_ddb.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: awin_ir.c,v 1.4 2014/11/15 14:56:18 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: awin_ir.c,v 1.5 2014/12/07 18:32:13 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -48,7 +50,7 @@
#include <dev/ir/cirio.h>
#include <dev/ir/cirvar.h>
-#define AWIN_IR_RXSTA_MASK __BITS(7,0)
+#define AWIN_IR_RXSTA_MASK __BITS(6,0)
struct awin_ir_softc {
device_t sc_dev;
@@ -116,13 +118,15 @@
struct awinio_attach_args * const aio = aux;
const struct awin_locators * const loc = &aio->aio_loc;
struct ir_attach_args iaa;
+ bus_space_handle_t bsh = awin_chip_id() == AWIN_CHIP_ID_A80 ?
+ aio->aio_a80_rcpus_bsh : aio->aio_core_bsh;
sc->sc_dev = self;
sc->sc_bst = aio->aio_core_bst;
sc->sc_port = loc->loc_port;
mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_IR);
cv_init(&sc->sc_cv, "awinir");
- bus_space_subregion(sc->sc_bst, aio->aio_core_bsh,
+ bus_space_subregion(sc->sc_bst, bsh,
loc->loc_offset, loc->loc_size, &sc->sc_bsh);
aprint_naive("\n");
@@ -187,7 +191,35 @@
AWIN_A31_PRCM_CIR_CLK_REG, clk);
bus_space_unmap(sc->sc_bst, prcm_bsh, prcm_size);
- } else {
+ } else if (awin_chip_id() == AWIN_CHIP_ID_A80) {
+ const struct awin_gpio_pinset pinset =
+ { 'L', AWIN_A80_PIO_PL_CIR_FUNC, AWIN_A80_PIO_PL_CIR_PINS,
+ GPIO_PIN_PULLUP };
+ bus_space_handle_t prcm_bsh;
+ bus_size_t prcm_size = 0x200;
+
+ bus_space_subregion(sc->sc_bst, aio->aio_a80_rcpus_bsh,
+ AWIN_A80_RPRCM_OFFSET, prcm_size, &prcm_bsh);
+
+ awin_gpio_pinset_acquire(&pinset);
+
+ awin_reg_set_clear(sc->sc_bst, prcm_bsh,
+ AWIN_A80_RPRCM_APB0_GATING_REG,
+ AWIN_A80_RPRCM_APB0_GATING_CIR, 0);
+ awin_reg_set_clear(sc->sc_bst, prcm_bsh,
+ AWIN_A80_RPRCM_APB0_RST_REG,
+ AWIN_A80_RPRCM_APB0_RST_CIR, 0);
+ awin_reg_set_clear(sc->sc_bst, prcm_bsh,
+ AWIN_A80_RPRCM_CIR_CLK_REG,
+ __SHIFTIN(AWIN_CLK_SRC_SEL_CIR_HOSC, AWIN_CLK_SRC_SEL) |
+ __SHIFTIN(7, AWIN_CLK_DIV_RATIO_M) |
+ __SHIFTIN(0, AWIN_CLK_DIV_RATIO_N) |
+ AWIN_CLK_ENABLE,
+ AWIN_CLK_SRC_SEL |
+ AWIN_CLK_DIV_RATIO_M | AWIN_CLK_DIV_RATIO_N);
+
+ bus_space_unmap(sc->sc_bst, prcm_bsh, prcm_size);
+ } else {
const struct awin_gpio_pinset pinset =
{ 'B', AWIN_PIO_PB_IR0_FUNC, AWIN_PIO_PB_IR0_PINS };
uint32_t clk;
@@ -253,7 +285,8 @@
cir |= __SHIFTIN(0, AWIN_IR_CIR_SCS2);
cir |= __SHIFTIN(8, AWIN_IR_CIR_NTHR);
cir |= __SHIFTIN(2, AWIN_IR_CIR_ITHR);
- if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ if (awin_chip_id() == AWIN_CHIP_ID_A31 ||
+ awin_chip_id() == AWIN_CHIP_ID_A80) {
cir |= __SHIFTIN(99, AWIN_IR_CIR_ATHR);
cir |= __SHIFTIN(0, AWIN_IR_CIR_ATHC);
}
@@ -264,6 +297,8 @@
IR_WRITE(sc, AWIN_IR_RXSTA_REG, AWIN_IR_RXSTA_MASK);
rxint = AWIN_IR_RXINT_RPEI_EN;
+ rxint |= AWIN_IR_RXINT_ROI_EN;
+ rxint |= AWIN_IR_RXINT_RAI_EN;
rxint |= __SHIFTIN(31, AWIN_IR_RXINT_RAL);
IR_WRITE(sc, AWIN_IR_RXINT_REG, rxint);
diff -r 7a158b8d4db5 -r 10d8692d36ee sys/arch/arm/allwinner/awin_reg.h
--- a/sys/arch/arm/allwinner/awin_reg.h Sun Dec 07 16:20:33 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_reg.h Sun Dec 07 18:32:13 2014 +0000
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