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[src/trunk]: src/sys/arch/arm/samsung 1st stage of USB support for Exynos5 ch...
details: https://anonhg.NetBSD.org/src/rev/7f07819d11f2
branches: trunk
changeset: 332004:7f07819d11f2
user: reinoud <reinoud%NetBSD.org@localhost>
date: Thu Sep 04 13:06:49 2014 +0000
description:
1st stage of USB support for Exynos5 chips: the register definitions
diffstat:
sys/arch/arm/samsung/exynos4_reg.h | 27 +++++++++++-
sys/arch/arm/samsung/exynos5_loc.c | 1 +
sys/arch/arm/samsung/exynos5_reg.h | 79 +++++++++++++++++++++++++++++++++++--
sys/arch/arm/samsung/exynos_reg.h | 27 +++---------
4 files changed, 107 insertions(+), 27 deletions(-)
diffs (203 lines):
diff -r 8941fe00a533 -r 7f07819d11f2 sys/arch/arm/samsung/exynos4_reg.h
--- a/sys/arch/arm/samsung/exynos4_reg.h Thu Sep 04 04:06:07 2014 +0000
+++ b/sys/arch/arm/samsung/exynos4_reg.h Thu Sep 04 13:06:49 2014 +0000
@@ -211,8 +211,9 @@
#define EXYNOS4_SROMC_OFFSET 0x02570000
#define EXYNOS4_USB2HOST_OFFSET 0x02580000
-#define EXYNOS4_USBHOST0_OFFSET 0x02580000 /* USB EHCI */
-#define EXYNOS4_USBHOST1_OFFSET 0x02590000 /* USB OHCI companion to EHCI (paired) */
+#define EXYNOS4_USB2_HOST_EHCI_OFFSET 0x02580000
+#define EXYNOS4_USB2_HOST_OHCI_OFFSET 0x02590000
+#define EXYNOS4_USB2_HOST_PHYCTRL_OFFSET 0x025B0000
#define EXYNOS4_USBOTG1_OFFSET 0x025B0000 /* USB On The Go interface */
#define EXYNOS4_PDMA0_OFFSET 0x02680000 /* Peripheral DMA */
@@ -273,6 +274,26 @@
#define EXYNOS4_GPIO_I2S0_OFFSET (EXYNOS4_AUDIOCORE_OFFSET + 0x00060000)
+/* used Exynos4 USB PHY registers */
+#define USB_PHYPWR 0x00
+#define PHYPWR_FORCE_SUSPEND __BIT(1)
+#define PHYPWR_ANALOG_POWERDOWN __BIT(3)
+#define PHYPWR_OTG_DISABLE __BIT(4)
+#define PHYPWR_SLEEP_PHY0 __BIT(5)
+#define PHYPWR_NORMAL_MASK 0x19
+#define PHYPWR_NORMAL_MASK_PHY0 (__BITS(3,3) | 1)
+#define PHYPWR_NORMAL_MASK_PHY1 __BITS(6,3)
+#define PHYPWR_NORMAL_MASK_HSIC0 __BITS(9,3)
+#define PHYPWR_NORMAL_MASK_HSIC1 __BITS(12,3)
+#define USB_PHYCLK 0x04 /* holds FSEL_CLKSEL_ */
+#define USB_RSTCON 0x08
+#define RSTCON_SWRST __BIT(0)
+#define RSTCON_HLINK_RWRST __BIT(1)
+#define RSTCON_DEVPHYLINK_SWRST __BIT(2)
+#define RSTCON_DEVPHY_SWRST __BITS(0,3)
+#define RSTCON_HOSTPHY_SWRST __BITS(3,4)
+#define RSTCON_HOSTPHYLINK_SWRST __BITS(7,4)
-#endif /* _ARM_SAMSUNG_EXYNOS5_REG_H_ */
+#endif /* _ARM_SAMSUNG_EXYNOS4_REG_H_ */
+
diff -r 8941fe00a533 -r 7f07819d11f2 sys/arch/arm/samsung/exynos5_loc.c
--- a/sys/arch/arm/samsung/exynos5_loc.c Thu Sep 04 04:06:07 2014 +0000
+++ b/sys/arch/arm/samsung/exynos5_loc.c Thu Sep 04 13:06:49 2014 +0000
@@ -220,6 +220,7 @@
{ "sscom", OFFANDSIZE(,UART1), 1, IRQ_UART1, 0 },
{ "sscom", OFFANDSIZE(,UART2), 2, IRQ_UART2, 0 },
{ "sscom", OFFANDSIZE(,UART3), 3, IRQ_UART3, 0 },
+ { "exyousb", OFFANDSIZE(,USB2HOST), NOPORT, IRQ_USB_HOST20, 0 },
};
const struct exyo_locinfo exynos5_locinfo = {
diff -r 8941fe00a533 -r 7f07819d11f2 sys/arch/arm/samsung/exynos5_reg.h
--- a/sys/arch/arm/samsung/exynos5_reg.h Thu Sep 04 04:06:07 2014 +0000
+++ b/sys/arch/arm/samsung/exynos5_reg.h Thu Sep 04 13:06:49 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos5_reg.h,v 1.13 2014/08/28 17:59:46 reinoud Exp $ */
+/* $NetBSD: exynos5_reg.h,v 1.14 2014/09/04 13:06:49 reinoud Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -55,17 +55,18 @@
#define EXYNOS5_CORE_SIZE 0x0f000000
#define EXYNOS5_SDRAM_PBASE 0x40000000
-#define EXYNOS5_CMU_COREPART_OFFSET 0x00010000
+#define EXYNOS5_CMU_CORE_PART_OFFSET 0x00010000
#define EXYNOS5_CMU_APLL 0x00010000 /* ARM core clock */
#define EXYNOS5_CMU_MPLL 0x00014000 /* MEM cntr. clock */
-#define EXYNOS5_CMU_TOPPART_OFFSET 0x00020000
+#define EXYNOS5_CMU_TOP_PART_OFFSET 0x00020000
#define EXYNOS5_CMU_CPLL 0x00020020 /* Video hardware codec clock */
#define EXYNOS5_CMU_EPLL 0x00020030 /* Audio and ext. interf. clock */
#define EXYNOS5_CMU_VPLL 0x00020040 /* Dither PLL (EMI reduction) clock */
#define EXYNOS5_CMU_GPLL 0x00020050 /* Graphic 3D proc. clock */
-#define EXYNOS5_CMU_MEMPART_OFFSET 0x00030000
+#define EXYNOS5_CMU_MEM_PART_OFFSET 0x00030000
#define EXYNOS5_CMU_BPLL 0x00030010
#define EXYNOS5_ALIVE_OFFSET 0x00040000
+#define EXYNOS5_PMU_OFFSET 0x00040000 /* alias */
#define EXYNOS5_SYSREG_OFFSET 0x00050000
#define EXYNOS5_TMU_OFFSET 0x00060000
#define EXYNOS5_MONOTONIC_CNT_OFFSET 0x000C0000
@@ -135,7 +136,7 @@
#define EXYNOS5_USB2HOST_OFFSET 0x02110000
#define EXYNOS5_USB2_HOST_EHCI_OFFSET 0x02110000
#define EXYNOS5_USB2_HOST_OHCI_OFFSET 0x02120000
-#define EXYNOS5_USB2_HOST_CTRL_OFFSET 0x02130000
+#define EXYNOS5_USB2_HOST_PHYCTRL_OFFSET 0x02130000
#define EXYNOS5_USB2_DEVICE_LINK_OFFSET 0x02140000
#define EXYNOS5_MIPI_HSI_OFFSET 0x02160000
@@ -357,4 +358,72 @@
#define EXYNOS5_GPIO_I2S_OFFSET (EXYNOS5_CORE_SIZE + 0x00060000)
#define EXYNOS5_AUDIOCORE_SIZE 0x00070000
+
+/* used Exynos5 USB PHY registers */
+#define USB_PHY_HOST_CTRL0 0x00
+#define HOST_CTRL0_PHY_SWRST __BIT(0)
+#define HOST_CTRL0_LINK_SWRST __BIT(1)
+#define HOST_CTRL0_UTMI_SWRST __BIT(2)
+#define HOST_CTRL0_WORDINTERFACE __BIT(3)
+#define HOST_CTRL0_FORCESUSPEND __BIT(4)
+#define HOST_CTRL0_FORCESLEEP __BIT(5)
+#define HOST_CTRL0_SIDDQ __BIT(6)
+#define HOST_CTRL0_COMMONON_N __BIT(9) /* common block configuration during suspend */
+#define HOST_CTRL0_TESTBURNIN __BIT(11)
+#define HOST_CTRL0_RETENABLE __BIT(10)
+#define HOST_CTRL0_FSEL_MASK __BITS(16, 18) /* holds FSEL_CLKSEL_ */
+#define HOST_CTRL0_REFCLKSEL_MASK __BITS(19, 20)
+#define HOST_CTRL0_REFCLKSEL_XTAL __SHIFTIN(HOST_CRTL0_REFCLK_MASK, 0)
+#define HOST_CTRL0_REFCLKSEL_EXTL __SHIFTIN(HOST_CRTL0_REFCLK_MASK, 1)
+#define HOST_CTRL0_REFCLKSEL_CLKCORE __SHIFTIN(HOST_CRTL0_REFCLK_MASK, 2)
+#define HOST_CTRL0_PHYSWRSTALL __BIT(31)
+
+#define USB_PHY_HSIC_CTRL1 0x10
+#define USB_PHY_HSIC_TUNE1 0x14
+#define USB_PHY_HSIC_CTRL2 0x20
+#define USB_PHY_HSIC_TUNE2 0x24
+#define HSIC_CTRL_PHY_SWRST __BIT(0)
+#define HSIC_CTRL_UTMI_SWRST __BIT(2)
+#define HSIC_CTRL_WORDINTERFACE __BIT(3)
+#define HSIC_CTRL_FORCESUSPEND __BIT(4)
+#define HSIC_CTRL_FORCESLEEP __BIT(5)
+#define HSIC_CTRL_SIDDQ __BIT(6)
+#define HSIC_CTRL_REFCLKDIV_MASK __BITS(16,22)
+#define REFCLKDIV_12 __SHIFTIN(HSIC_CTRL_REFCLKDIV_MASK, 0x24)
+#define REFCLKDIV_15 __SHIFTIN(HSIC_CTRL_REFCLKDIV_MASK, 0x1c)
+#define REFCLKDIV_16 __SHIFTIN(HSIC_CTRL_REFCLKDIV_MASK, 0x1a)
+#define REFCLKDIV_19_2 __SHIFTIN(HSIC_CTRL_REFCLKDIV_MASK, 0x15)
+#define REFCLKDIV_20 __SHIFTIN(HSIC_CTRL_REFCLKDIV_MASK, 0x14)
+#define HSIC_CTRL_REFCLKSEL_MASK __BITS(23, 24)
+#define REFCLKSEL_HSIC_DEFAULT __SHIFTIN(HSIC_CTRL_REFCLKSEL_MASK, 2)
+
+#define USB_PHY_HOST_EHCICTRL 0x30
+#define HOST_EHCICTRL_ENA_INCR16 __BIT(26)
+#define HOST_EHCICTRL_ENA_INCR8 __BIT(27)
+#define HOST_EHCICTRL_ENA_INCR4 __BIT(28)
+#define HOST_EHCICTRL_ENA_INCRXALIGN __BIT(29)
+
+#define USB_PHY_HOST_OHCICTRL 0x34
+#define HOST_OHCICTRL_CLKCK_RST __BIT(0)
+#define HOST_OHCICTRL_CNTSEL __BIT(1)
+#define HOST_OHCICTRL_APPSTARTCLK __BIT(2)
+#define HOST_OHCICTRL_SUSPLGCY __BIT(3)
+
+#define USB_PHY_OTG_SYS 0x38
+#define OTG_SYS_FORCESUSPEND __BIT(0)
+#define OTG_SYS_SIDDQ_UOTG __BIT(1)
+#define OTG_SYS_OTGDISABLE __BIT(2)
+#define OTG_SYS_FORCESLEEP __BIT(3)
+#define OTG_SYS_FSEL_MASK __BITS(4, 6) /* holds FSEL_CLKSEL_ */
+#define OTG_SYS_COMMON_ON __BIT(7)
+#define OTG_SYS_IDPULLUP_UOTG __BIT(8)
+#define OTG_SYS_REFCLKSEL_MASK __BITS(9, 10)
+#define OTG_SYS_REFCLKSEL_XTAL __SHIFTIN(OTG_SYS_REFCLKSEL_MASK, 0)
+#define OTG_SYS_REFCLKSEL_EXTL __SHIFTIN(OTG_SYS_REFCLKSEL_MASK, 1)
+#define OTG_SYS_REFCLKSEL_CLKCORE __SHIFTIN(OTG_SYS_REFCLKSEL_MASK, 2)
+#define OTG_SYS_PHY0_SWRST __BIT(12)
+#define OTG_SYS_LINK_SWRST_UOTG __BIT(13)
+#define OTG_SYS_PHYLINK_SWRST __BIT(14)
+
+
#endif /* _ARM_SAMSUNG_EXYNOS5_REG_H_ */
diff -r 8941fe00a533 -r 7f07819d11f2 sys/arch/arm/samsung/exynos_reg.h
--- a/sys/arch/arm/samsung/exynos_reg.h Thu Sep 04 04:06:07 2014 +0000
+++ b/sys/arch/arm/samsung/exynos_reg.h Thu Sep 04 13:06:49 2014 +0000
@@ -186,24 +186,13 @@
#define EXYNOS5_SYSREG_USB20_PHY_TYPE 0x230
-/* used USB PHY registers */
-#define USB_PHYPWR 0x00
-#define PHYPWR_FORCE_SUSPEND __BIT(1)
-#define PHYPWR_ANALOG_POWERDOWN __BIT(3)
-#define PHYPWR_OTG_DISABLE __BIT(4)
-#define PHYPWR_SLEEP_PHY0 __BIT(5)
-#define PHYPWR_NORMAL_MASK 0x19
-#define PHYPWR_NORMAL_MASK_PHY0 (__BITS(3,3) | 1)
-#define PHYPWR_NORMAL_MASK_PHY1 __BITS(6,3)
-#define PHYPWR_NORMAL_MASK_HSIC0 __BITS(9,3)
-#define PHYPWR_NORMAL_MASK_HSIC1 __BITS(12,3)
-#define USB_PHYCLK 0x04
-#define USB_RSTCON 0x08
-#define RSTCON_SWRST __BIT(0)
-#define RSTCON_HLINK_RWRST __BIT(1)
-#define RSTCON_DEVPHYLINK_SWRST __BIT(2)
-#define RSTCON_DEVPHY_SWRST __BITS(0,3)
-#define RSTCON_HOSTPHY_SWRST __BITS(3,4)
-#define RSTCON_HOSTPHYLINK_SWRST __BITS(7,4)
+/* Generic USB registers/constants */
+#define FSEL_CLKSEL_50M 7
+#define FSEL_CLKSEL_24M 5
+#define FSEL_CLKSEL_20M 4
+#define FSEL_CLKSEL_19200K 3
+#define FSEL_CLKSEL_12M 2
+#define FSEL_CLKSEL_10M 1
+#define FSEL_CLKSEL_9600K 0
#endif /* _ARM_SAMSUNG_EXYNOS_REG_H_ */
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