[src/trunk]: src/sys/arch/arm/allwinner CIR regs

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/bf26f859b10a
branches:  trunk
changeset: 333420:bf26f859b10a
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sun Nov 02 23:54:46 2014 +0000

description:
CIR regs

diffstat:

 sys/arch/arm/allwinner/awin_reg.h |  96 ++++++++++++++++++++++++++++++++++++++-
 1 files changed, 94 insertions(+), 2 deletions(-)

diffs (132 lines):

diff -r 022a7840e0e4 -r bf26f859b10a sys/arch/arm/allwinner/awin_reg.h
--- a/sys/arch/arm/allwinner/awin_reg.h Sun Nov 02 23:54:16 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_reg.h Sun Nov 02 23:54:46 2014 +0000
@@ -755,6 +755,88 @@
 } __packed;
 #endif
 
+#define AWIN_IR_CTL_REG                        0x0000
+#define AWIN_IR_TXCTL_REG              0x0004
+#define AWIN_IR_TXADR_REG              0x0008
+#define AWIN_IR_TXCNT_REG              0x000C
+#define AWIN_IR_RXCTL_REG              0x0010
+#define AWIN_IR_RXADR_REG              0x0014
+#define AWIN_IR_RXCNT_REG              0x0018
+#define AWIN_IR_TXFIFO_REG             0x001C
+#define AWIN_IR_RXFIFO_REG             0x0020
+#define AWIN_IR_TXINT_REG              0x0024
+#define AWIN_IR_TXSTA_REG              0x0028
+#define AWIN_IR_RXINT_REG              0x002C
+#define AWIN_IR_RXSTA_REG              0x0030
+#define AWIN_IR_CIR_REG                        0x0034
+
+#define AWIN_IR_CTL_CGPO               __BIT(8)
+#define AWIN_IR_CTL_MD                 __BITS(5,4)
+#define AWIN_IR_CTL_MD_0_576_MIR       0
+#define AWIN_IR_CTL_MD_1_152_MIR       1
+#define AWIN_IR_CTL_MD_4_0_FIR         2
+#define AWIN_IR_CTL_MD_CIR             3
+#define AWIN_IR_CTL_TXEN               __BIT(2)
+#define AWIN_IR_CTL_RXEN               __BIT(1)
+#define AWIN_IR_CTL_GEN                        __BIT(0)
+
+#define AWIN_IR_TXCTL_PCF              __BIT(5)
+#define AWIN_IR_TXCTL_SIP              __BIT(3)
+#define AWIN_IR_TXCTL_TPPI             __BIT(2)
+
+#define AWIN_IR_TXADR_HAG              __BIT(8)
+#define AWIN_IR_TXADR_TPA              __BITS(7,0)
+
+#define AWIN_IR_TXCNT_TPL              __BITS(10,0)
+
+#define AWIN_IR_RXCTL_RPA              __BIT(3)
+#define AWIN_IR_RXCTL_RPPI             __BIT(2)
+
+#define AWIN_IR_RXADR_RAM              __BIT(8)
+#define AWIN_IR_RXADR_RA               __BITS(7,0)
+
+#define AWIN_IR_RXCNT_RPL              __BITS(11,0)
+
+#define AWIN_IR_TXFIFO_DATA            __BITS(7,0)
+
+#define AWIN_IR_RXFIFO_DATA            __BITS(7,0)
+
+#define AWIN_IR_TXINT_TEL              __BITS(11,8)
+#define AWIN_IR_TXINT_DRQ_EN           __BIT(5)
+#define AWIN_IR_TXINT_TEI_EN           __BIT(4)
+#define AWIN_IR_TXINT_TCI_EN           __BIT(3)
+#define AWIN_IR_TXINT_SIPEI_EN         __BIT(2)
+#define AWIN_IR_TXINT_TPEI_EN          __BIT(1)
+#define AWIN_IR_TUI_EN                 __BIT(0)
+
+#define AWIN_IR_TXSTA_TA               __BITS(12,8)
+#define AWIN_IR_TXSTA_TE               __BIT(4)
+#define AWIN_IR_TXSTA_TC               __BIT(3)
+#define AWIN_IR_TXSTA_SIPE             __BIT(2)
+#define AWIN_IR_TXSTA_TPE              __BIT(1)
+#define AWIN_IR_TXSTA_TU               __BIT(0)
+
+#define AWIN_IR_RXINT_RAL              __BITS(11,8)
+#define AWIN_IR_RXINT_DRQ_EN           __BIT(5)
+#define AWIN_IR_RXINT_RAI_EN           __BIT(4)
+#define AWIN_IR_RXINT_CRCI_EN          __BIT(3)
+#define AWIN_IR_RXINT_RISI_EN          __BIT(2)
+#define AWIN_IR_RXINT_RPEI_EN          __BIT(1)
+#define AWIN_IR_RXINT_ROI_EN           __BIT(0)
+
+#define AWIN_IR_RXSTA_RAC              __BITS(12,8)
+#define AWIN_IR_RXSTA_STAT             __BIT(7)        /* A31 */
+#define AWIN_IR_RXSTA_RA               __BIT(4)
+#define AWIN_IR_RXSTA_CRC              __BIT(3)
+#define AWIN_IR_RXSTA_RIS              __BIT(2)
+#define AWIN_IR_RXSTA_RPE              __BIT(1)
+#define AWIN_IR_RXSTA_ROI              __BIT(0)
+
+#define AWIN_IR_CIR_SCS2               __BIT(24)
+#define AWIN_IR_CIR_ITHR               __BITS(15,8)
+#define AWIN_IR_CIR_NTHR               __BITS(7,2)
+#define AWIN_IR_CIR_SCS                        __BITS(1,0)
+
 #define AWIN_CPUCFG_CPU0_RST_CTRL_REG  0x0040
 #define AWIN_CPUCFG_CPU0_CTRL_REG      0x0044
 #define AWIN_CPUCFG_CPU0_STATUS_REG    0x0048
@@ -1701,13 +1783,17 @@
 #define AWIN_A31_USB2_OFFSET           0x0001b000      /* EHCI1/OHCI1 */
 #define AWIN_A31_USB3_OFFSET           0x0001c000      /* OHCI2 */
 #define AWIN_A31_GMAC_OFFSET           0x00030000      /* GMAC */
+#define AWIN_A31_RTC_OFFSET            0x00300000      /* RTC */
 #define AWIN_A31_PRCM_OFFSET           0x00301400      /* PRCM */
 #define AWIN_A31_CPUCFG_OFFSET         0x00301C00
-#define AWIN_A31_RTC_OFFSET            0x00300000      /* RTC */
+#define AWIN_A31_CIR_OFFSET            0x00302000      /* CIR */
 #define AWIN_A31_CPUPIO_OFFSET         0x00302c00      /* CPUs-PORT */
 #define AWIN_A31_P2WI_OFFSET           0x00303400      /* P2WI */
 
-#define AWIN_A31_PRCM_PWROFF_GATING_REG                0x100
+#define AWIN_A31_PRCM_APB0_GATING_REG          0x0028
+#define AWIN_A31_PRCM_CIR_CLK_REG              0x0054
+#define AWIN_A31_PRCM_APB0_RESET_REG           0x00B0
+#define AWIN_A31_PRCM_PWROFF_GATING_REG                0x0100
 #define AWIN_A31_PRCM_CPUX_PWR_CLAMP_REG       0x0140
 #define AWIN_A31_PRCM_CPU1_PWR_CLAMP_REG       0x0144
 #define AWIN_A31_PRCM_CPU2_PWR_CLAMP_REG       0x0148
@@ -1728,6 +1814,10 @@
 #define AWIN_A31_AHB_RESET2_REG                0x02C8
 #define AWIN_A31_APB1_RESET_REG                0x02D0
 
+#define AWIN_A31_PRCM_APB0_GATING_CIR  __BIT(1)
+
+#define AWIN_A31_PRCM_APB0_RESET_CIR   __BIT(1)
+
 #define AWIN_A31_CPUCFG_RST_CTRL_CORE_RESET __BIT(1)
 #define AWIN_A31_CPUCFG_RST_CTRL_CPU_RESET __BIT(0)
 
@@ -1987,6 +2077,8 @@
 #define AWIN_A31_PIO_PH_TWI2_PINS      0x000c0000 /* PH pins 19-18 */
 
 #define AWIN_A31_PIO_PL_PINS           9
+#define AWIN_A31_PIO_PL_IR_FUNC                2
+#define AWIN_A31_PIO_PL_IR_PINS                0x00000010 /* PL pin 4 */
 
 #define AWIN_A31_PIO_PM_PINS           8