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[src/trunk]: src/sys/arch/arm/allwinner Start of the 10/100 driver.
details: https://anonhg.NetBSD.org/src/rev/ffdf8d0dad00
branches: trunk
changeset: 329707:ffdf8d0dad00
user: matt <matt%NetBSD.org@localhost>
date: Thu Jun 05 03:48:08 2014 +0000
description:
Start of the 10/100 driver.
diffstat:
sys/arch/arm/allwinner/awin_eth.c | 596 ++++++++++++++++++++++++++++++++++++-
1 files changed, 579 insertions(+), 17 deletions(-)
diffs (truncated from 712 to 300 lines):
diff -r e10571b60ef0 -r ffdf8d0dad00 sys/arch/arm/allwinner/awin_eth.c
--- a/sys/arch/arm/allwinner/awin_eth.c Thu Jun 05 03:46:26 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_eth.c Thu Jun 05 03:48:08 2014 +0000
@@ -31,12 +31,15 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_eth.c,v 1.3 2013/09/08 04:06:44 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_eth.c,v 1.4 2014/06/05 03:48:08 matt Exp $");
+#include <sys/param.h>
#include <sys/bus.h>
#include <sys/device.h>
#include <sys/intr.h>
+#include <sys/ioctl.h>
#include <sys/mutex.h>
+#include <sys/rnd.h>
#include <sys/systm.h>
#include <net/if.h>
@@ -51,10 +54,47 @@
static int awin_eth_match(device_t, cfdata_t, void *);
static void awin_eth_attach(device_t, device_t, void *);
+static int awin_eth_intr(void *);
+
static int awin_eth_miibus_read_reg(device_t, int, int);
static void awin_eth_miibus_write_reg(device_t, int, int, int);
static void awin_eth_miibus_statchg(struct ifnet *);
+static void awin_eth_ifstart(struct ifnet *);
+static int awin_eth_ifioctl(struct ifnet *, u_long, void *);
+static int awin_eth_ifinit(struct ifnet *);
+static void awin_eth_ifstop(struct ifnet *, int);
+static void awin_eth_ifwatchdog(struct ifnet *);
+static void awin_eth_ifdrain(struct ifnet *);
+
+struct awin_eth_softc;
+static void awin_eth_rx_hash(struct awin_eth_softc *);
+
+struct awin_eth_regs {
+ uint32_t reg_ctl;
+ uint32_t reg_ts_mode;
+ uint32_t reg_ts_flow;
+ uint32_t reg_ts_ctl[2];
+ uint32_t reg_ts_ins;
+ uint32_t reg_ts_pl[2];
+ uint32_t reg_ts_sta;
+ uint32_t reg_rx_ctl;
+ uint32_t reg_rx_hash[2];
+ uint32_t reg_rx_sta;
+ uint32_t reg_rx_fbc;
+ uint32_t reg_int_ctl;
+ uint32_t reg_mac_ctl0;
+ uint32_t reg_mac_ctl1;
+ uint32_t reg_mac_ipgt;
+ uint32_t reg_mac_ipgr;
+ uint32_t reg_mac_clrt;
+ uint32_t reg_mac_maxf;
+ uint32_t reg_mac_supp;
+ uint32_t reg_mac_a0;
+ uint32_t reg_mac_a1;
+ uint32_t reg_mac_a2;
+};
+
struct awin_eth_softc {
device_t sc_dev;
bus_space_tag_t sc_bst;
@@ -62,7 +102,12 @@
bus_dma_tag_t sc_dmat;
struct ethercom sc_ec;
struct mii_data sc_mii;
+ krndsource_t sc_rnd_source; /* random source */
+ kmutex_t sc_intr_lock;
kmutex_t sc_mdio_lock;
+ uint8_t sc_tx_active;
+ struct awin_eth_regs sc_reg;
+ void *sc_ih;
};
CFATTACH_DECL_NEW(awin_eth, sizeof(struct awin_eth_softc),
@@ -74,17 +119,25 @@
};
static inline uint32_t
-awin_eth_read_4(struct awin_eth_softc *sc, bus_size_t o)
+awin_eth_read(struct awin_eth_softc *sc, bus_size_t o)
{
return bus_space_read_4(sc->sc_bst, sc->sc_bsh, o);
}
static inline void
-awin_eth_write_4(struct awin_eth_softc *sc, bus_size_t o, uint32_t v)
+awin_eth_write(struct awin_eth_softc *sc, bus_size_t o, uint32_t v)
{
return bus_space_write_4(sc->sc_bst, sc->sc_bsh, o, v);
}
+static inline void
+awin_eth_clear_set(struct awin_eth_softc *sc, bus_size_t o, uint32_t c,
+ uint32_t s)
+{
+ uint32_t v = bus_space_read_4(sc->sc_bst, sc->sc_bsh, o);
+ return bus_space_write_4(sc->sc_bst, sc->sc_bsh, o, (v & ~c) | s);
+}
+
static int
awin_eth_match(device_t parent, cfdata_t cf, void *aux)
{
@@ -116,11 +169,22 @@
&awin_eth_pinsets[cf->cf_flags & 1];
struct ifnet * const ifp = &sc->sc_ec.ec_if;
struct mii_data * const mii = &sc->sc_mii;
+ char enaddr[ETHER_ADDR_LEN];
sc->sc_dev = self;
awin_gpio_pinset_acquire(pinset);
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_AHB_GATING0_REG, AWIN_AHB_GATING0_EMAC, 0);
+ /*
+ * Give 13KB of SRAM to EMAC
+ */
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_core_bsh,
+ AWIN_SRAM_OFFSET + AWIN_SRAM_CTL1_REG,
+ __SHIFTIN(AWIN_SRAM_CTL1_A3_A4_EMAC, AWIN_SRAM_CTL1_A3_A4),
+ AWIN_SRAM_CTL1_A3_A4);
+ mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_NET);
mutex_init(&sc->sc_mdio_lock, MUTEX_DEFAULT, IPL_NET);
sc->sc_bst = aio->aio_core_bst;
@@ -131,7 +195,40 @@
aprint_naive("\n");
aprint_normal(": 10/100 Ethernet Controller\n");
+ /*
+ * Diable and then clear all interrupts
+ */
+ awin_eth_write(sc, AWIN_EMAC_INT_CTL_REG, 0);
+ awin_eth_write(sc, AWIN_EMAC_INT_STA_REG,
+ awin_eth_read(sc, AWIN_EMAC_INT_STA_REG));
+
+ sc->sc_ih = intr_establish(loc->loc_intr, IPL_NET, IST_LEVEL,
+ awin_eth_intr, sc);
+ if (sc->sc_ih == NULL) {
+ aprint_error_dev(self, "failed to establish interrupt %d\n",
+ loc->loc_intr);
+ return;
+ }
+ aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
+
+ uint32_t a1 = awin_eth_read(sc, AWIN_EMAC_MAC_A1_REG);
+ uint32_t a0 = awin_eth_read(sc, AWIN_EMAC_MAC_A0_REG);
+ if (a0 != 0 || a1 != 0) {
+ enaddr[0] = a1 >> 16;
+ enaddr[1] = a1 >> 8;
+ enaddr[2] = a1 >> 0;
+ enaddr[3] = a0 >> 16;
+ enaddr[4] = a0 >> 8;
+ enaddr[5] = a0 >> 0;
+ }
+
ifp->if_softc = sc;
+ ifp->if_start = awin_eth_ifstart;
+ ifp->if_ioctl = awin_eth_ifioctl;
+ ifp->if_init = awin_eth_ifinit;
+ ifp->if_stop = awin_eth_ifstop;
+ ifp->if_watchdog = awin_eth_ifwatchdog;
+ ifp->if_drain = awin_eth_ifdrain;
ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus);
@@ -140,9 +237,8 @@
mii->mii_writereg = awin_eth_miibus_write_reg;
mii->mii_statchg = awin_eth_miibus_statchg;
- int mii_flags = 0;
-
- mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, mii_flags);
+ mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY,
+ MIIF_DOPAUSE);
if (LIST_EMPTY(&mii->mii_phys)) {
aprint_error_dev(self, "no PHY found!\n");
@@ -151,6 +247,14 @@
} else {
ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO);
}
+
+ /*
+ * Attach the interface.
+ */
+ if_attach(ifp);
+ ether_ifattach(ifp, enaddr);
+ rnd_attach_source(&sc->sc_rnd_source, device_xname(self),
+ RND_TYPE_NET, 0);
}
int
@@ -160,13 +264,13 @@
mutex_enter(&sc->sc_mdio_lock);
- awin_eth_write_4(sc, AWIN_EMAC_MAC_MADR_REG, (phy << 8) | reg);
- awin_eth_write_4(sc, AWIN_EMAC_MAC_MCMD_REG, 1);
+ awin_eth_write(sc, AWIN_EMAC_MAC_MADR_REG, (phy << 8) | reg);
+ awin_eth_write(sc, AWIN_EMAC_MAC_MCMD_REG, 1);
delay(100);
- awin_eth_write_4(sc, AWIN_EMAC_MAC_MCMD_REG, 0);
- const uint32_t rv = awin_eth_read_4(sc, AWIN_EMAC_MAC_MRDD_REG);
+ awin_eth_write(sc, AWIN_EMAC_MAC_MCMD_REG, 0);
+ const uint32_t rv = awin_eth_read(sc, AWIN_EMAC_MAC_MRDD_REG);
mutex_exit(&sc->sc_mdio_lock);
@@ -180,13 +284,13 @@
mutex_enter(&sc->sc_mdio_lock);
- awin_eth_write_4(sc, AWIN_EMAC_MAC_MADR_REG, (phy << 8) | reg);
- awin_eth_write_4(sc, AWIN_EMAC_MAC_MCMD_REG, 1);
+ awin_eth_write(sc, AWIN_EMAC_MAC_MADR_REG, (phy << 8) | reg);
+ awin_eth_write(sc, AWIN_EMAC_MAC_MCMD_REG, 1);
delay(100);
- awin_eth_write_4(sc, AWIN_EMAC_MAC_MCMD_REG, 0);
- awin_eth_write_4(sc, AWIN_EMAC_MAC_MWTD_REG, val);
+ awin_eth_write(sc, AWIN_EMAC_MAC_MCMD_REG, 0);
+ awin_eth_write(sc, AWIN_EMAC_MAC_MWTD_REG, val);
mutex_exit(&sc->sc_mdio_lock);
}
@@ -196,14 +300,472 @@
{
struct awin_eth_softc * const sc = ifp->if_softc;
struct mii_data * const mii = &sc->sc_mii;
+ const u_int media = mii->mii_media_active;
/*
- * Set MII or GMII interface based on the speed
+ * Set MII interface based on the speed
* negotiated by the PHY.
*/
- switch (IFM_SUBTYPE(mii->mii_media_active)) {
+ switch (IFM_SUBTYPE(media)) {
case IFM_10_T:
+ sc->sc_reg.reg_mac_supp &= ~AWIN_EMAC_MAC_SUPP_100M;
+ break;
case IFM_100_TX:
- ;
+ sc->sc_reg.reg_mac_supp |= AWIN_EMAC_MAC_SUPP_100M;
+ break;
+ }
+
+ sc->sc_reg.reg_mac_ctl0 &=
+ ~(AWIN_EMAC_MAC_CTL0_TFC|AWIN_EMAC_MAC_CTL0_RFC);
+ if (media & IFM_FLOW) {
+ if (media & IFM_ETH_TXPAUSE) {
+ sc->sc_reg.reg_mac_ctl0 |= AWIN_EMAC_MAC_CTL0_TFC;
+ }
+ if (media & IFM_ETH_RXPAUSE) {
+ sc->sc_reg.reg_mac_ctl0 |= AWIN_EMAC_MAC_CTL0_RFC;
+ }
+ }
+
+ sc->sc_reg.reg_mac_ctl1 &= ~AWIN_EMAC_MAC_CTL1_FD;
+ if (media & IFM_FDX) {
+ sc->sc_reg.reg_mac_ctl1 |= AWIN_EMAC_MAC_CTL1_FD;
+ }
+}
+
+static inline void
+awin_eth_int_enable(struct awin_eth_softc *sc)
+{
+ awin_eth_clear_set(sc, AWIN_EMAC_INT_CTL_REG, 0,
+ AWIN_EMAC_INT_RX|AWIN_EMAC_INT_TX0|AWIN_EMAC_INT_TX1);
+}
+
+static inline void
+awin_eth_rxfifo_flush(struct awin_eth_softc *sc)
+{
+ uint32_t rxctl_reg = awin_eth_read(sc, AWIN_EMAC_RX_CTL_REG);
+
+ if (rxctl_reg & AWIN_EMAC_RX_CTL_DMA) {
+ awin_eth_write(sc, AWIN_EMAC_RX_CTL_REG,
+ rxctl_reg & ~AWIN_EMAC_RX_CTL_DMA);
+ }
+ awin_eth_write(sc, AWIN_EMAC_RX_CTL_REG,
+ (rxctl_reg & ~AWIN_EMAC_RX_CTL_DMA)
+ | AWIN_EMAC_RX_CTL_FIFO_RESET);
+
+ for (;;) {
+ uint32_t v0 = awin_eth_read(sc, AWIN_EMAC_RX_CTL_REG);
+ if ((v0 & AWIN_EMAC_RX_CTL_FIFO_RESET) == 0)
+ break;
+ }
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