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[src/trunk]: src/sys/arch/mips/ralink Add PCI register definitions



details:   https://anonhg.NetBSD.org/src/rev/e44e59d7e157
branches:  trunk
changeset: 328825:e44e59d7e157
user:      matt <matt%NetBSD.org@localhost>
date:      Sat Apr 19 12:48:03 2014 +0000

description:
Add PCI register definitions

diffstat:

 sys/arch/mips/ralink/ralink_reg.h |  1102 +++++++++++++++++++-----------------
 1 files changed, 584 insertions(+), 518 deletions(-)

diffs (truncated from 1382 to 300 lines):

diff -r 5d180cf320e2 -r e44e59d7e157 sys/arch/mips/ralink/ralink_reg.h
--- a/sys/arch/mips/ralink/ralink_reg.h Sat Apr 19 12:46:04 2014 +0000
+++ b/sys/arch/mips/ralink/ralink_reg.h Sat Apr 19 12:48:03 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ralink_reg.h,v 1.4 2012/02/12 01:51:52 oki Exp $       */
+/*     $NetBSD: ralink_reg.h,v 1.5 2014/04/19 12:48:03 matt Exp $      */
 /*-
  * Copyright (c) 2011 CradlePoint Technology, Inc.
  * All rights reserved.
@@ -36,76 +36,80 @@
 #include <mips/cpuregs.h>
 
 #if defined(RT3050)
-#define RA_CLOCK_RATE          320000000
-#define RA_BUS_FREQ            (RA_CLOCK_RATE / 3)
-#define RA_UART_FREQ           RA_BUS_FREQ
+#define RA_CLOCK_RATE          320000000
+#define RA_BUS_FREQ            (RA_CLOCK_RATE / 3)
+#define RA_UART_FREQ           RA_BUS_FREQ
 #elif defined(RT3052)
-#define RA_CLOCK_RATE          384000000
-#define RA_BUS_FREQ            (RA_CLOCK_RATE / 3)
-#define RA_UART_FREQ           RA_BUS_FREQ
+#define RA_CLOCK_RATE          384000000
+#define RA_BUS_FREQ            (RA_CLOCK_RATE / 3)
+#define RA_UART_FREQ           RA_BUS_FREQ
 #elif defined(RT3883)
 #if 0
-#define RA_CLOCK_RATE          480000000
+#define RA_CLOCK_RATE          480000000
 #else
-#define RA_CLOCK_RATE          500000000
+#define RA_CLOCK_RATE          500000000
 #endif
-#define RA_BUS_FREQ            166000000 /* DDR speed */
-#define RA_UART_FREQ           40000000
+#define RA_BUS_FREQ            166000000 /* DDR speed */
+#define RA_UART_FREQ           40000000
 #else
 /* Ralink dev board */
-#define RA_CLOCK_RATE          384000000
-#define RA_BUS_FREQ            (RA_CLOCK_RATE / 3)
-#define RA_UART_FREQ           RA_BUS_FREQ
+#define RA_CLOCK_RATE          384000000
+#define RA_BUS_FREQ            (RA_CLOCK_RATE / 3)
+#define RA_UART_FREQ           RA_BUS_FREQ
 #endif
 
-#define RA_BAUDRATE            CONSPEED
-#define RA_SERIAL_CLKDIV       16
+#define RA_BAUDRATE            CONSPEED
+#define RA_SERIAL_CLKDIV       16
 
-#define RA_SRAM_BASE           0x00000000
-#define RA_SRAM_END            0x0FFFFFFF
-#define RA_SYSCTL_BASE         0x10000000
-#define RA_TIMER_BASE          0x10000100
-#define RA_INTCTL_BASE         0x10000200
-#define RA_MEMCTL_BASE         0x10000300
+#define RA_SRAM_BASE           0x00000000
+#define RA_SRAM_END            0x0FFFFFFF
+#define RA_SYSCTL_BASE         0x10000000
+#define RA_TIMER_BASE          0x10000100
+#define RA_INTCTL_BASE         0x10000200
+#define RA_MEMCTL_BASE         0x10000300
 #if defined(RT3052) || defined(RT3050)
-#define RA_PCM_BASE            0x10000400
+#define RA_PCM_BASE            0x10000400
 #endif
-#define RA_UART_BASE           0x10000500
-#define RA_PIO_BASE            0x10000600
+#define RA_UART_BASE           0x10000500
+#define RA_PIO_BASE            0x10000600
 #if defined(RT3052) || defined(RT3050)
-#define RA_GDMA_BASE           0x10000700
+#define RA_GDMA_BASE           0x10000700
 #elif defined(RT3883)
-#define RA_FLASHCTL_BASE       0x10000700
+#define RA_FLASHCTL_BASE       0x10000700
 #endif
-#define RA_NANDCTL_BASE        0x10000800
-#define RA_I2C_BASE            0x10000900
-#define RA_I2S_BASE            0x10000A00
-#define RA_SPI_BASE            0x10000B00
-#define RA_UART_LITE_BASE      0x10000C00
+#define RA_NANDCTL_BASE        0x10000800
+#define RA_I2C_BASE            0x10000900
+#define RA_I2S_BASE            0x10000A00
+#define RA_SPI_BASE            0x10000B00
+#define RA_UART_LITE_BASE      0x10000C00
 #if defined(RT3883)
-#define RA_PCM_BASE            0x10002000
-#define RA_GDMA_BASE           0x10002800
-#define RA_CODEC1_BASE         0x10003000
-#define RA_CODEC2_BASE         0x10003800
+#define RA_PCM_BASE            0x10002000
+#define RA_GDMA_BASE           0x10002800
+#define RA_CODEC1_BASE         0x10003000
+#define RA_CODEC2_BASE         0x10003800
 #endif
-#define RA_FRAME_ENGINE_BASE   0x10100000
-#define RA_ETH_SW_BASE         0x10110000
-#define RA_ROM_BASE            0x10118000
-#if defined(RT3883)
-#define RA_USB_DEVICE_BASE     0x10120000
-#define RA_PCI_BASE            0x10140000
+#define RA_FRAME_ENGINE_BASE   0x10100000
+#define RA_ETH_SW_BASE         0x10110000
+#define RA_ROM_BASE            0x10118000
+#if defined(RT3883) || defined(MT7620)
+#define RA_USB_DEVICE_BASE     0x10120000
+#if defined(MT7620)
+#define RA_SDHC_BASE           0x10130000
 #endif
-#define RA_11N_MAC_BASE        0x10180000
-#define RA_USB_OTG_BASE        0x101C0000
-#if defined(RT3883)
-#define RA_USB_HOST_BASE       0x101C0000
+#define RA_PCI_BASE            0x10140000
+#define RA_PCIWIN_BASE         0x10150000
+#endif
+#define RA_11N_MAC_BASE                0x10180000
+#define RA_USB_OTG_BASE                0x101C0000
+#if defined(RT3883) || defined(MT7620)
+#define RA_USB_HOST_BASE       0x101C0000
 #endif
 #if defined(RT3052) || defined(RT3050)
-#define RA_FLASH_BASE          0x1F000000
-#define RA_FLASH_END           0x1F7FFFFF
+#define RA_FLASH_BASE          0x1F000000
+#define RA_FLASH_END           0x1F7FFFFF
 #elif defined(RT3883) 
-#define RA_FLASH_BASE          0x1C000000
-#define RA_FLASH_END           0x1DFFFFFF
+#define RA_FLASH_BASE          0x1C000000
+#define RA_FLASH_END           0x1DFFFFFF
 #endif
 
 #define RA_IOREG_VADDR(base, offset)   \
@@ -117,15 +121,16 @@
 /*
  * System Control Registers
  */
-#define RA_SYSCTL_ID0          0x00
-#define RA_SYSCTL_ID1          0x04
-#define RA_SYSCTL_CFG0         0x10
-#define RA_SYSCTL_CFG1         0x14
-#define RA_SYSCTL_CLKCFG0      0x2C
-#define RA_SYSCTL_CLKCFG1      0x30
-#define RA_SYSCTL_RST          0x34
-#define RA_SYSCTL_RSTSTAT      0x38
-#define RA_SYSCTL_GPIOMODE     0x60
+#define RA_SYSCTL_ID0                  0x00
+#define RA_SYSCTL_ID1                  0x04
+#define RA_SYSCTL_REVID                        0x0c
+#define RA_SYSCTL_CFG0                 0x10
+#define RA_SYSCTL_CFG1                 0x14
+#define RA_SYSCTL_CLKCFG0              0x2C
+#define RA_SYSCTL_CLKCFG1              0x30
+#define RA_SYSCTL_RST                  0x34
+#define RA_SYSCTL_RSTSTAT              0x38
+#define RA_SYSCTL_GPIOMODE             0x60
 
 #if defined(RT3050) || defined(RT3052)
 #define        SYSCTL_CFG0_INIC_EE_SDRAM       __BIT(29)
@@ -138,188 +143,208 @@
 #define        SYSCTL_CFG0_TEST_CODE           __BITS(8,15)
 #define        SYSCTL_CFG0_SRAM_CS_MODE        __BITS(2,3)
 #define        SYSCTL_CFG0_SDRAM_CLK_DRV       __BIT(0)
-#else
-#define        SYSCTL_CFG0_BE          __BIT(19)
-#define SYSCTL_CFG0_DRAM_SIZE  __BITS(12,14) 
-#define        SYSCTL_CFG0_DRAM_2MB    0
-#define        SYSCTL_CFG0_DRAM_8MB    1
-#define        SYSCTL_CFG0_DRAM_16MB   2
-#define        SYSCTL_CFG0_DRAM_32MB   3
-#define        SYSCTL_CFG0_DRAM_64MB   4
-#define        SYSCTL_CFG0_DRAM_128MB  5
-#define        SYSCTL_CFG0_DRAM_256MB  6
+#elif defined(RT3883)
+#define        SYSCTL_CFG0_BE                  __BIT(19)
+#define SYSCTL_CFG0_DRAM_SIZE          __BITS(12,14) 
+#define        SYSCTL_CFG0_DRAM_2MB            0
+#define        SYSCTL_CFG0_DRAM_8MB            1
+#define        SYSCTL_CFG0_DRAM_16MB           2
+#define        SYSCTL_CFG0_DRAM_32MB           3
+#define        SYSCTL_CFG0_DRAM_64MB           4
+#define        SYSCTL_CFG0_DRAM_128MB          5
+#define        SYSCTL_CFG0_DRAM_256MB          6
+#elif defined(MT7620)
+#define        SYSCTL_CFG0_TEST_CODE           __BITS(31,24)
+#define        SYSCTL_CFG0_BS_SHADOW           __BITS(22,12)
+#define        SYSCTL_CFG0_DRAM_FROM_EE        __BIT(8)
+#define        SYSCTL_CFG0_DBG_JTAG_MODE       __BIT(7)
+#define        SYSCTL_CFG0_XTAL_FREQ_SEL       __BIT(6)
+#define        SYSCTL_CFG0_DRAM_TYPE           __BITS(5,4)
+#define        SYSCTL_CFG0_CHIP_MODE           __BITS(3,0)
 #endif
 
-#if defined(RT3883)
+#if defined(RT3883) || defined(MT7620)
 /* 3883 doesn't have memo regs, use teststat instead */
-#define RA_SYSCTL_MEMO0        0x18
-#define RA_SYSCTL_MEMO1        0x1C
+#define RA_SYSCTL_MEMO0        0x18
+#define RA_SYSCTL_MEMO1        0x1C
 #else
-#define RA_SYSCTL_MEMO0        0x68
-#define RA_SYSCTL_MEMO1        0x6C
+#define RA_SYSCTL_MEMO0        0x68
+#define RA_SYSCTL_MEMO1        0x6C
 #endif
 
-#define  RST_SW        (1 << 23)
-#define  RST_OTG       (1 << 22)
-#define  RST_FE        (1 << 21)
-#define  RST_WLAN      (1 << 20)
-#define  RST_UARTL     (1 << 19)
-#define  RST_SPI       (1 << 18)
-#define  RST_I2S       (1 << 17)
-#define  RST_I2C       (1 << 16)
-#define  RST_NAND      (1 << 15)
-#define  RST_DMA       (1 << 14)
-#define  RST_PIO       (1 << 13)
-#define  RST_UART      (1 << 12)
-#define  RST_PCM       (1 << 11)
-#define  RST_MC        (1 << 10)
-#define  RST_INTC      (1 << 9)
-#define  RST_TIMER     (1 << 8)
-#define  RST_SYS       (1 << 0)
-#define  GPIOMODE_RGMII  (1 << 9)
-#define  GPIOMODE_SDRAM  (1 << 8)
-#define  GPIOMODE_MDIO   (1 << 7)
-#define  GPIOMODE_JTAG   (1 << 6)
-#define  GPIOMODE_UARTL  (1 << 5)
-#define  GPIOMODE_UARTF2 (1 << 4)
-#define  GPIOMODE_UARTF1 (1 << 3)
-#define  GPIOMODE_UARTF0 (1 << 2)
+#define  RST_PPE               __BIT(31)
+#define  RST_SDHC              __BIT(30)
+#define  RST_MIPS_CNT          __BIT(28)
+#define  RST_PCIE0             __BIT(26)
+#define  RST_UHST0             __BIT(25)
+#define  RST_EPHY              __BIT(24)
+#define  RST_SW                        __BIT(23)
+#define  RST_OTG               __BIT(22)
+#define  RST_FE                        __BIT(21)
+#define  RST_WLAN              __BIT(20)
+#define  RST_UARTL             __BIT(19)
+#define  RST_SPI               __BIT(18)
+#define  RST_I2S               __BIT(17)
+#define  RST_I2C               __BIT(16)
+#define  RST_NAND              __BIT(15)
+#define  RST_DMA               __BIT(14)
+#define  RST_PIO               __BIT(13)
+#define  RST_UART              __BIT(12)
+#define  RST_PCM               __BIT(11)
+#define  RST_MC                        __BIT(10)
+#define  RST_INTC              __BIT(9)
+#define  RST_TIMER             __BIT(8)
+#define  RST_GE2               __BIT(7)
+#define  RST_GE1               __BIT(6)
+#define  RST_SYS               __BIT(0)
+#define  GPIOMODE_RGMII                __BIT(9)
+#define  GPIOMODE_SDRAM                __BIT(8)
+#define  GPIOMODE_MDIO         __BIT(7)
+#define  GPIOMODE_JTAG         __BIT(6)
+#define  GPIOMODE_UARTL                __BIT(5)
+#define  GPIOMODE_UARTF2       __BIT(4)
+#define  GPIOMODE_UARTF1       __BIT(3)
+#define  GPIOMODE_UARTF0       __BIT(2)
 #define  GPIOMODE_UARTF_0_2    \
-                        (GPIOMODE_UARTF0|GPIOMODE_UARTF1|GPIOMODE_UARTF2)
-#define  GPIOMODE_SPI    (1 << 1)
-#define  GPIOMODE_I2C    (1 << 0)
+               (GPIOMODE_UARTF0|GPIOMODE_UARTF1|GPIOMODE_UARTF2)
+#define  GPIOMODE_SPI          __BIT(1)
+#define  GPIOMODE_I2C          __BIT(0)
 
 /*
  * Timer Registers
  */
-#define RA_TIMER_STAT          0x00
-#define RA_TIMER_0_LOAD        0x10
-#define RA_TIMER_0_VALUE       0x14
-#define RA_TIMER_0_CNTRL       0x18
-#define RA_TIMER_1_LOAD        0x20
-#define RA_TIMER_1_VALUE       0x24
-#define RA_TIMER_1_CNTRL       0x28
+#define RA_TIMER_STAT          0x00
+#define RA_TIMER_0_LOAD                0x10
+#define RA_TIMER_0_VALUE       0x14
+#define RA_TIMER_0_CNTRL       0x18
+#define RA_TIMER_1_LOAD                0x20
+#define RA_TIMER_1_VALUE       0x24
+#define RA_TIMER_1_CNTRL       0x28
 
-#define  TIMER_1_RESET         (1 << 5)
-#define  TIMER_0_RESET         (1 << 4)
-#define  TIMER_1_INT_STATUS    (1 << 1)



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