[src/trunk]: src/sys/arch/arm/include/arm32 Make to flush the secondary cache...

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/055e20d64132
branches:  trunk
changeset: 328743:055e20d64132
user:      matt <matt%NetBSD.org@localhost>
date:      Wed Apr 16 07:29:52 2014 +0000

description:
Make to flush the secondary cache when syncing PTEs when the Sheeva L2 cache
is used.

diffstat:

 sys/arch/arm/include/arm32/pmap.h |  9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)

diffs (24 lines):

diff -r 363d75ab43d7 -r 055e20d64132 sys/arch/arm/include/arm32/pmap.h
--- a/sys/arch/arm/include/arm32/pmap.h Wed Apr 16 02:22:38 2014 +0000
+++ b/sys/arch/arm/include/arm32/pmap.h Wed Apr 16 07:29:52 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.h,v 1.131 2014/04/11 04:19:47 matt Exp $  */
+/*     $NetBSD: pmap.h,v 1.132 2014/04/16 07:29:52 matt Exp $  */
 
 /*
  * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@@ -503,8 +503,13 @@
 static inline void
 pmap_ptesync(pt_entry_t *ptep, size_t cnt)
 {
-       if (PMAP_NEEDS_PTE_SYNC)
+       if (PMAP_NEEDS_PTE_SYNC) {
                cpu_dcache_wb_range((vaddr_t)ptep, cnt * sizeof(pt_entry_t));
+#ifdef SHEEVA_L2_CACHE
+               cpu_sdcache_wb_range((vaddr_t)ptep, -1,
+                   cnt * sizeof(pt_entry_t));
+#endif
+       }
 #if ARM_MMU_V7 > 0
        __asm("dsb");
 #endif