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[src/trunk]: src/sys/arch/arm Various MP changes.
details: https://anonhg.NetBSD.org/src/rev/2be76ffc1895
branches: trunk
changeset: 328168:2be76ffc1895
user: matt <matt%NetBSD.org@localhost>
date: Fri Mar 28 21:39:09 2014 +0000
description:
Various MP changes.
diffstat:
sys/arch/arm/arm32/arm32_boot.c | 52 +++++++++---
sys/arch/arm/arm32/arm32_machdep.c | 33 ++-----
sys/arch/arm/arm32/cpu.c | 109 +++++++++++++++++--------
sys/arch/arm/cortex/gic.c | 84 ++++++++++++++++---
sys/arch/arm/cortex/gic_reg.h | 12 ++-
sys/arch/arm/include/locore.h | 40 ++++++++-
sys/arch/arm/vfp/vfp_init.c | 156 +++++++++++++++---------------------
7 files changed, 300 insertions(+), 186 deletions(-)
diffs (truncated from 917 to 300 lines):
diff -r 25b3dbfbe733 -r 2be76ffc1895 sys/arch/arm/arm32/arm32_boot.c
--- a/sys/arch/arm/arm32/arm32_boot.c Fri Mar 28 21:32:41 2014 +0000
+++ b/sys/arch/arm/arm32/arm32_boot.c Fri Mar 28 21:39:09 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: arm32_boot.c,v 1.6 2014/03/03 08:52:30 matt Exp $ */
+/* $NetBSD: arm32_boot.c,v 1.7 2014/03/28 21:39:09 matt Exp $ */
/*
* Copyright (c) 2002, 2003, 2005 Genetec Corporation. All rights reserved.
@@ -123,7 +123,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.6 2014/03/03 08:52:30 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.7 2014/03/28 21:39:09 matt Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@@ -132,6 +132,8 @@
#include <sys/reboot.h>
#include <sys/cpu.h>
#include <sys/intr.h>
+#include <sys/atomic.h>
+#include <sys/device.h>
#include <uvm/uvm_extern.h>
@@ -320,19 +322,34 @@
*/
splhigh();
+#ifdef VERBOSE_INIT_ARM
printf("%s(%s): ", __func__, ci->ci_data.cpu_name);
+#endif
+ uint32_t mpidr = armreg_mpidr_read();
+ if (mpidr & MPIDR_MT) {
+ ci->ci_data.cpu_smt_id = mpidr & MPIDR_AFF0;
+ ci->ci_data.cpu_core_id = mpidr & MPIDR_AFF1;
+ ci->ci_data.cpu_package_id = mpidr & MPIDR_AFF2;
+ } else {
+ ci->ci_data.cpu_core_id = mpidr & MPIDR_AFF0;
+ ci->ci_data.cpu_package_id = mpidr & MPIDR_AFF1;
+ }
/*
* Make sure we have the right vector page.
*/
+#ifdef VERBOSE_INIT_ARM
printf(" vectors");
+#endif
arm32_vector_init(systempage.pv_va, ARM_VEC_ALL);
/*
- * Initialize the stack for each mode (we are already running on the SVC32
- * stack of the idlelwp).
+ * Initialize the stack for each mode (we are already running on the
+ * SVC32 stack of the idlelwp).
*/
+#ifdef VERBOSE_INIT_ARM
printf(" stacks");
+#endif
set_stackptr(PSR_FIQ32_MODE,
fiqstack.pv_va + cpu_index(ci) * FIQ_STACK_SIZE * PAGE_SIZE);
set_stackptr(PSR_IRQ32_MODE,
@@ -345,13 +362,14 @@
ci->ci_lastlwp = NULL;
ci->ci_pmap_lastuser = NULL;
#ifdef ARM_MMU_EXTENDED
+#ifdef VERBOSE_INIT_ARM
printf(" tlb");
+#endif
/*
* Attach to the tlb.
*/
ci->ci_pmap_cur = pmap_kernel();
ci->ci_pmap_asid_cur = KERNEL_PID;
- pmap_tlb_info_attach(&pmap_tlb0_info, ci);
#endif
#ifdef CPU_CORTEX
@@ -364,24 +382,32 @@
}
#endif
+ aprint_naive("%s", device_xname(ci->ci_dev));
+ aprint_normal("%s", device_xname(ci->ci_dev));
+ identify_arm_cpu(ci->ci_dev, ci);
+#ifdef VERBOSE_INIT_ARM
+ printf(" vfp");
+#endif
+ vfp_attach(ci);
+
+#ifdef VERBOSE_INIT_ARM
printf(" interrupts");
+#endif
/*
* Let the interrupts do what they need to on this CPU.
*/
intr_cpu_init(ci);
+#ifdef VERBOSE_INIT_ARM
printf(" md(%p)", md_cpu_init);
+#endif
if (md_cpu_init != NULL)
(*md_cpu_init)(ci);
-#if 0
- /*
- * Tell the MI code we are alive!
- */
- printf(" mi_cpu");
- mi_cpu_running(ci);
+#ifdef VERBOSE_INIT_ARM
+ printf(" done!\n");
#endif
-
- printf(" done!\n");
+ atomic_and_32(&arm_cpu_mbox, ~(1 << cpuid));
+ __asm __volatile("sev; sev; sev");
}
#endif /* MULTIPROCESSOR */
diff -r 25b3dbfbe733 -r 2be76ffc1895 sys/arch/arm/arm32/arm32_machdep.c
--- a/sys/arch/arm/arm32/arm32_machdep.c Fri Mar 28 21:32:41 2014 +0000
+++ b/sys/arch/arm/arm32/arm32_machdep.c Fri Mar 28 21:39:09 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: arm32_machdep.c,v 1.101 2014/03/03 08:15:36 matt Exp $ */
+/* $NetBSD: arm32_machdep.c,v 1.102 2014/03/28 21:39:09 matt Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@@ -42,7 +42,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.101 2014/03/03 08:15:36 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.102 2014/03/28 21:39:09 matt Exp $");
#include "opt_modular.h"
#include "opt_md.h"
@@ -683,16 +683,17 @@
void
cpu_boot_secondary_processors(void)
{
- uint32_t mbox;
- kcpuset_export_u32(kcpuset_attached, &mbox, sizeof(mbox));
-#ifdef VERBOSE_ARM_INIT
- printf("%s: writing mbox with %#x\n", __func__, mbox);
+#ifdef VERBOSE_INIT_ARM
+ printf("%s: writing mbox with %#x\n", __func__, arm_cpu_hatched);
#endif
- atomic_swap_32(&arm_cpu_mbox, mbox);
+ arm_cpu_mbox = arm_cpu_hatched;
membar_producer();
#ifdef _ARM_ARCH_7
__asm __volatile("sev; sev; sev");
#endif
+ while (arm_cpu_mbox) {
+ __asm("wfe");
+ }
}
void
@@ -701,23 +702,7 @@
KASSERT(kpreempt_disabled());
KASSERT(curcpu() != ci);
-
- if (ci) {
- /* Unicast, remote CPU */
- printf("%s: -> %s", __func__, ci->ci_data.cpu_name);
- intr_ipi_send(ci->ci_kcpuset, IPI_XCALL);
- } else {
- printf("%s: -> !%s", __func__, ci->ci_data.cpu_name);
- /* Broadcast to all but ourselves */
- kcpuset_t *kcp;
- kcpuset_create(&kcp, (ci != NULL));
- KASSERT(kcp != NULL);
- kcpuset_copy(kcp, kcpuset_running);
- kcpuset_clear(kcp, cpu_index(ci));
- intr_ipi_send(kcp, IPI_XCALL);
- kcpuset_destroy(kcp);
- }
- printf("\n");
+ intr_ipi_send(ci != NULL ? ci->ci_kcpuset : NULL, IPI_XCALL);
}
#endif /* MULTIPROCESSOR */
diff -r 25b3dbfbe733 -r 2be76ffc1895 sys/arch/arm/arm32/cpu.c
--- a/sys/arch/arm/arm32/cpu.c Fri Mar 28 21:32:41 2014 +0000
+++ b/sys/arch/arm/arm32/cpu.c Fri Mar 28 21:39:09 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.103 2014/03/24 20:06:31 christos Exp $ */
+/* $NetBSD: cpu.c,v 1.104 2014/03/28 21:39:09 matt Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -46,7 +46,7 @@
#include <sys/param.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.103 2014/03/24 20:06:31 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.104 2014/03/28 21:39:09 matt Exp $");
#include <sys/systm.h>
#include <sys/conf.h>
@@ -64,15 +64,15 @@
#ifdef MULTIPROCESSOR
volatile u_int arm_cpu_hatched = 0;
-u_int arm_cpu_max = 0;
-uint32_t arm_cpu_mbox __cacheline_aligned = 0;
-uint32_t arm_cpu_marker[2] __cacheline_aligned = { 0, 0 };
+volatile uint32_t arm_cpu_mbox __cacheline_aligned = 0;
+uint32_t arm_cpu_marker[2] __cacheline_aligned = { 0, 0 };
+u_int arm_cpu_max = 1;
#endif
/* Prototypes */
-void identify_arm_cpu(device_t dv, struct cpu_info *);
-void identify_cortex_caches(device_t dv);
-void identify_features(device_t dv);
+void identify_arm_cpu(device_t, struct cpu_info *);
+void identify_cortex_caches(device_t);
+void identify_features(device_t);
/*
* Identify the master (boot) CPU
@@ -99,11 +99,22 @@
KASSERT(ci != NULL);
ci->ci_cpl = IPL_HIGH;
ci->ci_cpuid = id;
+ uint32_t mpidr = armreg_mpidr_read();
+ if (mpidr & MPIDR_MT) {
+ ci->ci_data.cpu_smt_id = mpidr & MPIDR_AFF0;
+ ci->ci_data.cpu_core_id = mpidr & MPIDR_AFF1;
+ ci->ci_data.cpu_package_id = mpidr & MPIDR_AFF2;
+ } else {
+ ci->ci_data.cpu_core_id = mpidr & MPIDR_AFF0;
+ ci->ci_data.cpu_package_id = mpidr & MPIDR_AFF1;
+ }
ci->ci_data.cpu_core_id = id;
ci->ci_data.cpu_cc_freq = cpu_info_store.ci_data.cpu_cc_freq;
ci->ci_arm_cpuid = cpu_info_store.ci_arm_cpuid;
ci->ci_arm_cputype = cpu_info_store.ci_arm_cputype;
ci->ci_arm_cpurev = cpu_info_store.ci_arm_cpurev;
+ ci->ci_ctrl = cpu_info_store.ci_ctrl;
+ ci->ci_undefsave[2] = cpu_info_store.ci_undefsave[2];
cpu_info[ci->ci_cpuid] = ci;
if ((arm_cpu_hatched & (1 << id)) == 0) {
ci->ci_dev = dv;
@@ -157,15 +168,27 @@
NULL, xname, "permission abort (S)");
evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_PERM_P], EVCNT_TYPE_TRAP,
NULL, xname, "permission abort (P)");
+ evcnt_attach_dynamic_nozero(&ci->ci_und_ev, EVCNT_TYPE_TRAP,
+ NULL, xname, "undefined insn traps");
+ evcnt_attach_dynamic_nozero(&ci->ci_und_cp15_ev, EVCNT_TYPE_TRAP,
+ NULL, xname, "undefined cp15 insn traps");
#ifdef MULTIPROCESSOR
/*
* and we are done if this is a secondary processor.
*/
- if (!CPU_IS_PRIMARY(ci)) {
+ if (id != 0) {
+#if 1
+ aprint_naive("\n");
+ aprint_normal("\n");
+#else
aprint_naive(": %s\n", cpu_getmodel());
aprint_normal(": %s\n", cpu_getmodel());
+#endif
mi_cpu_attach(ci);
+#ifdef ARM_MMU_EXTENDED
+ pmap_tlb_info_attach(&pmap_tlb0_info, ci);
+#endif
return;
}
#endif
@@ -204,7 +227,7 @@
}
#endif
- vfp_attach(); /* XXX SMP */
+ vfp_attach(ci); /* XXX SMP */
}
enum cpu_class {
@@ -585,48 +608,58 @@
}
}
+static enum cpu_class
+identify_arm_model(uint32_t cpuid, char *buf, size_t len)
+{
+ enum cpu_class cpu_class = CPU_CLASS_NONE;
+ for (const struct cpuidtab *id = cpuids; id->cpuid != 0; id++) {
+ if (id->cpuid == (cpuid & CPU_ID_CPU_MASK)) {
+ const char *steppingstr =
+ id->cpu_steppings[cpuid & CPU_ID_REVISION_MASK];
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